X-Git-Url: https://sigrok.org/gitweb/?p=pulseview.git;a=blobdiff_plain;f=pv%2Fdata%2Flogicsegment.cpp;h=707f797d294accad64b5ee12f1ecd1551049344d;hp=3896ff2151efc09989d34211b78399f017473c88;hb=97cb532f668dd78a5100abb07d7500cbd36b6198;hpb=1ec3e43f7489cae3a9ca43e665044c8717f345f1

diff --git a/pv/data/logicsegment.cpp b/pv/data/logicsegment.cpp
index 3896ff21..707f797d 100644
--- a/pv/data/logicsegment.cpp
+++ b/pv/data/logicsegment.cpp
@@ -64,7 +64,7 @@ LogicSegment::~LogicSegment()
 		free(l.data);
 }
 
-uint64_t LogicSegment::unpack_sample(const uint8_t *ptr) const
+inline uint64_t LogicSegment::unpack_sample(const uint8_t *ptr) const
 {
 #ifdef HAVE_UNALIGNED_LITTLE_ENDIAN_ACCESS
 	return *(uint64_t*)ptr;
@@ -102,7 +102,7 @@ uint64_t LogicSegment::unpack_sample(const uint8_t *ptr) const
 #endif
 }
 
-void LogicSegment::pack_sample(uint8_t *ptr, uint64_t value)
+inline void LogicSegment::pack_sample(uint8_t *ptr, uint64_t value)
 {
 #ifdef HAVE_UNALIGNED_LITTLE_ENDIAN_ACCESS
 	*(uint64_t*)ptr = value;