Initial support for SRD_OUTPUT_LOGIC

[pulseview.git] / pv / data / logicsegment.hpp

diff --git a/pv/data/logicsegment.hpp b/pv/data/logicsegment.hpp
index 2e37ed2d248df56c22d1e0d1cd703d7835425fcb..2b67c0edb81ddad6165597499bf4d704d185a483 100644 (file)
--- a/pv/data/logicsegment.hpp
+++ b/pv/data/logicsegment.hpp
@@ -86,6 +86,18 @@ public:
        void append_payload(shared_ptr<sigrok::Logic> logic);
        void append_payload(void *data, uint64_t data_size);
 
+       /**
+        * Appends sample data for a single channel where each byte
+        * represents one sample - if it's 0 the state is low, if 1 high.
+        * Other values are not permitted.
+        * Assumes that all channels are having samples added and in the
+        * order of 0..n, not n..0.
+        * Also assumes the the number of samples added for each channel
+        * is constant for every invokation for 0..n. The number of samples
+        * hence may only change when index is 0.
+        */
+       void append_subsignal_payload(unsigned int index, void *data, uint64_t data_size);
+
        void get_samples(int64_t start_sample, int64_t end_sample, uint8_t* dest) const;
 
        /**