From: Uwe Hermann Date: Thu, 24 Nov 2011 08:35:26 +0000 (+0100) Subject: srd: i2c.py: Convert to new API (unfinished). X-Git-Tag: libsigrokdecode-0.1.0~264 X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=commitdiff_plain;h=f39d2404acb54461f61b676ab164d42e9e76e3fa srd: i2c.py: Convert to new API (unfinished). This decoder is probably not fully converted yet, and doesn't really successfully decode I2C, yet. It's work in progress. --- diff --git a/decoders/i2c.py b/decoders/i2c.py index 874e735..a46ba6a 100644 --- a/decoders/i2c.py +++ b/decoders/i2c.py @@ -125,139 +125,161 @@ # 'signals': [{'SCL': }]} # -def decode(l): - print(l) - sigrok.put(l) - -def decode2(inbuf): - """I2C protocol decoder""" - - # FIXME: Get the data in the correct format in the first place. - inbuf = [ord(x) for x in inbuf] - - # FIXME: This should be passed in as metadata, not hardcoded here. - metadata = { - 'numchannels': 8, - 'signals': { - 'scl': {'ch': 5, 'name': 'SCL', 'desc': 'Serial clock line'}, - 'sda': {'ch': 7, 'name': 'SDA', 'desc': 'Serial data line'}, - }, +class Sample(): + def __init__(self, data): + self.data = data + def probe(self, probe): + s = ord(self.data[probe / 8]) & (1 << (probe % 8)) + return True if s else False + +def sampleiter(data, unitsize): + for i in range(0, len(data), unitsize): + yield(Sample(data[i:i+unitsize])) + +class Decoder(): + name = 'I2C' + longname = 'Inter-Integrated Circuit (I2C) bus' + desc = 'I2C is a two-wire, multi-master, serial bus.' + longdesc = '...' + author = 'Uwe Hermann' + email = 'uwe@hermann-uwe.de' + license = 'gplv2+' + inputs = ['logic'] + outputs = ['i2c'] + probes = { + 'scl': {'ch': 0, 'name': 'SCL', 'desc': 'Serial clock line'}, + 'sda': {'ch': 1, 'name': 'SDA', 'desc': 'Serial data line'}, + } + options = { + 'address-space': ['Address space (in bits)', 7], } - out = [] - o = ack = d = '' - bitcount = data = 0 - wr = startsample = -1 - IDLE, START, ADDRESS, DATA = range(4) - state = IDLE - - # Get the channel/probe number of the SCL/SDA signals. - scl_bit = metadata['signals']['scl']['ch'] - sda_bit = metadata['signals']['sda']['ch'] - - # Get SCL/SDA bit values (0/1 for low/high) of the first sample. - s = inbuf[0] - oldscl = (s & (1 << scl_bit)) >> scl_bit - oldsda = (s & (1 << sda_bit)) >> sda_bit - - # Loop over all samples. - # TODO: Handle LAs with more/less than 8 channels. - for samplenum, s in enumerate(inbuf[1:]): # We skip the first byte... - # Get SCL/SDA bit values (0/1 for low/high). - scl = (s & (1 << scl_bit)) >> scl_bit - sda = (s & (1 << sda_bit)) >> sda_bit - - # TODO: Wait until the bus is idle (SDA = SCL = 1) first? - - # START condition (S): SDA = falling, SCL = high - if (oldsda == 1 and sda == 0) and scl == 1: - o = {'type': 'S', 'range': (samplenum, samplenum), - 'data': None, 'ann': None}, - out.append(o) - state = ADDRESS - bitcount = data = 0 - - # Data latching by transmitter: SCL = low - elif (scl == 0): - pass # TODO - - # Data sampling of receiver: SCL = rising - elif (oldscl == 0 and scl == 1): - if startsample == -1: - startsample = samplenum - bitcount += 1 - - # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \ - # (samplenum, 8 - bitcount, sda)) - - # Address and data are transmitted MSB-first. - data <<= 1 - data |= sda - - if bitcount != 9: + def __init__(self, unitsize, **kwargs): + # Metadata comes in here, we don't care for now. + # print kwargs + self.unitsize = unitsize + + self.probes = Decoder.probes.copy() + + # TODO: Don't hardcode the number of channels. + self.channels = 8 + + self.samplenum = 0 + + self.bitcount = 0 + self.databyte = 0 + self.wr = -1 + self.startsample = -1 + self.IDLE, self.START, self.ADDRESS, self.DATA = range(4) + self.state = self.IDLE + + # Get the channel/probe number of the SCL/SDA signals. + self.scl_bit = self.probes['scl']['ch'] + self.sda_bit = self.probes['sda']['ch'] + + self.oldscl = None + self.oldsda = None + + def report(self): + pass + + def decode(self, data): + """I2C protocol decoder""" + + out = [] + o = ack = d = '' + + # We should accept a list of samples and iterate... + for sample in sampleiter(data["data"], self.unitsize): + + # TODO: Eliminate the need for ord(). + s = ord(sample.data) + + # TODO: Start counting at 0 or 1? + self.samplenum += 1 + + # First sample: Save SCL/SDA value. + if self.oldscl == None: + # Get SCL/SDA bit values (0/1 for low/high) of the first sample. + self.oldscl = (s & (1 << self.scl_bit)) >> self.scl_bit + self.oldsda = (s & (1 << self.sda_bit)) >> self.sda_bit continue - # We received 8 address/data bits and the ACK/NACK bit. - data >>= 1 # Shift out unwanted ACK/NACK bit here. - ack = (sda == 1) and 'N' or 'A' - d = (state == ADDRESS) and (data & 0xfe) or data - if state == ADDRESS: - wr = (data & 1) and 1 or 0 - state = DATA - o = {'type': state, - 'range': (startsample, samplenum - 1), - 'data': d, 'ann': None} - if state == ADDRESS and wr == 1: - o['type'] = 'AW' - elif state == ADDRESS and wr == 0: - o['type'] = 'AR' - elif state == DATA and wr == 1: - o['type'] = 'DW' - elif state == DATA and wr == 0: - o['type'] = 'DR' - out.append(o) - o = {'type': ack, 'range': (samplenum, samplenum), - 'data': None, 'ann': None} - out.append(o) - bitcount = data = startsample = 0 - startsample = -1 - - # STOP condition (P): SDA = rising, SCL = high - elif (oldsda == 0 and sda == 1) and scl == 1: - o = {'type': 'P', 'range': (samplenum, samplenum), - 'data': None, 'ann': None}, - out.append(o) - state = IDLE - wr = -1 - - # Save current SDA/SCL values for the next round. - oldscl = scl - oldsda = sda - - # FIXME: Just for testing... - return str(out) - -register = { - 'id': 'i2c', - 'name': 'I2C', - 'longname': 'Inter-Integrated Circuit (I2C) bus', - 'desc': 'I2C is a two-wire, multi-master, serial bus.', - 'longdesc': '...', - 'author': 'Uwe Hermann', - 'email': 'uwe@hermann-uwe.de', - 'license': 'gplv2+', - 'in': ['logic'], - 'out': ['i2c'], - 'probes': [ - ['scl', 'Serial clock line'], - ['sda', 'Serial data line'], - ], - 'options': { - 'address-space': ['Address space (in bits)', 7], - }, - # 'start': start, - # 'report': report, -} + # Get SCL/SDA bit values (0/1 for low/high). + scl = (s & (1 << self.scl_bit)) >> self.scl_bit + sda = (s & (1 << self.sda_bit)) >> self.sda_bit + + # TODO: Wait until the bus is idle (SDA = SCL = 1) first? + + # START condition (S): SDA = falling, SCL = high + if (self.oldsda == 1 and sda == 0) and scl == 1: + o = {'type': 'S', 'range': (self.samplenum, self.samplenum), + 'data': None, 'ann': None}, + out.append(o) + self.state = self.ADDRESS + self.bitcount = self.databyte = 0 + + # Data latching by transmitter: SCL = low + elif (scl == 0): + pass # TODO + + # Data sampling of receiver: SCL = rising + elif (self.oldscl == 0 and scl == 1): + if self.startsample == -1: + self.startsample = self.samplenum + self.bitcount += 1 + + # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \ + # (self.samplenum, 8 - bitcount, sda)) + + # Address and data are transmitted MSB-first. + self.databyte <<= 1 + self.databyte |= sda + + if self.bitcount != 9: + continue + + # We received 8 address/data bits and the ACK/NACK bit. + self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here. + ack = (sda == 1) and 'N' or 'A' + d = (self.state == self.ADDRESS) and (self.databyte & 0xfe) or self.databyte + if self.state == self.ADDRESS: + self.wr = (self.databyte & 1) and 1 or 0 + self.state = self.DATA + o = {'type': self.state, + 'range': (self.startsample, self.samplenum - 1), + 'data': d, 'ann': None} + if self.state == self.ADDRESS and self.wr == 1: + o['type'] = 'AW' + elif self.state == self.ADDRESS and self.wr == 0: + o['type'] = 'AR' + elif self.state == self.DATA and self.wr == 1: + o['type'] = 'DW' + elif self.state == self.DATA and self.wr == 0: + o['type'] = 'DR' + out.append(o) + o = {'type': ack, 'range': (self.samplenum, self.samplenum), + 'data': None, 'ann': None} + out.append(o) + self.bitcount = self.databyte = self.startsample = 0 + self.startsample = -1 + + # STOP condition (P): SDA = rising, SCL = high + elif (self.oldsda == 0 and sda == 1) and scl == 1: + o = {'type': 'P', 'range': (self.samplenum, self.samplenum), + 'data': None, 'ann': None}, + out.append(o) + self.state = self.IDLE + self.wr = -1 + + # Save current SDA/SCL values for the next round. + self.oldscl = scl + self.oldsda = sda + + # TODO: Which output format? + # TODO: How to only output something after the last chunk of data? + if out != []: + sigrok.put(out) # Use psyco (if available) as it results in huge performance improvements. try: @@ -266,3 +288,5 @@ try: except ImportError: pass +import sigrok +