From: Gerhard Sittig <redacted>
Date: Sun, 18 Jun 2017 13:51:35 +0000 (+0200)
Subject: usb_signalling: Move another edge detection to common backend code
X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=commitdiff_plain;h=c240da484645ab78b19c8a8e2938df67039660f0;hp=73dc48310c47f4e3ebb6ee6de67983603ddd3ea3

usb_signalling: Move another edge detection to common backend code

Rephrase how the 'WAIT IDLE' stage skips over all-low input signals.
Have the next high level on either line detected in common code.
---

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index c0e0141..ae0f651 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -329,9 +329,10 @@ class Decoder(srd.Decoder):
                 elif self.state == 'GET EOP':
                     self.get_eop(sym)
             elif self.state == 'WAIT IDLE':
+                # Skip "all-low" input. Wait for high level on either DP or DM.
                 pins = self.wait({'skip': 1})
-                if pins == (0, 0):
-                    continue
+                while not pins[0] and not pins[1]:
+                    pins = self.wait([{0: 'h'}, {1: 'h'}])
                 if self.samplenum - self.samplenum_lastedge > 1:
                     sym = symbols[self.options['signalling']][pins]
                     self.handle_idle(sym)