From: Bert Vermeulen <redacted>
Date: Mon, 30 Jan 2012 23:48:07 +0000 (+0100)
Subject: edid: properly deal with leading I2C crud + small fixes
X-Git-Tag: libsigrokdecode-0.1.0~80
X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=commitdiff_plain;h=2a706c20b73ea466a16c7f5ae6a8b0d44e470053;hp=6fff00eee1dd62477cd2708df480b985ef416a67

edid: properly deal with leading I2C crud + small fixes
---

diff --git a/decoders/edid/edid.py b/decoders/edid/edid.py
index b575f46..6d53bf1 100644
--- a/decoders/edid/edid.py
+++ b/decoders/edid/edid.py
@@ -107,6 +107,8 @@ class Decoder(srd.Decoder):
         self.cnt += 1
         self.sn.append( [ss, es] )
         self.cache.append(data)
+        # debug
+#        self.put(ss, es, self.out_ann, [0, ["%d: [%.2x]" % (self.cnt, data)]])
 
         if self.state is None:
             # Wait for the EDID header
@@ -115,6 +117,7 @@ class Decoder(srd.Decoder):
                     # Throw away any garbage before the header
                     self.sn = self.sn[-8:]
                     self.cache = self.cache[-8:]
+                    self.cnt = 8
                     self.state = 'edid'
                     self.put(ss, es, self.out_ann, [0, ["EDID header"]])
         elif self.state == 'edid':
@@ -401,7 +404,7 @@ class Decoder(srd.Decoder):
                     + (posneg[sync2 & 0x01]) + ')'
         elif sync == 0x03:
             features += 'digital separate ('
-            features += 'Vsync polarity ' + (posneg[sync2 >> 1])
+            features += 'Vsync polarity ' + (posneg[(sync2 & 0x02) >> 1])
             features += ', Hsync polarity ' + (posneg[sync2 & 0x01])
             features += ')'
         features += ', '