From: Uwe Hermann <redacted>
Date: Wed, 21 Nov 2012 21:27:13 +0000 (+0100)
Subject: tlc5620: Refactoring, add initial LOAD support.
X-Git-Tag: libsigrokdecode-0.1.1~23
X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=commitdiff_plain;h=17db40087cb0b4ed76ee26cbc69458f598630fc6;ds=sidebyside

tlc5620: Refactoring, add initial LOAD support.
---

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 71bfb2c..757c304 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -53,13 +53,13 @@ class Decoder(srd.Decoder):
     ]
 
     def __init__(self, **kwargs):
-        self.state = 'IDLE'
-        self.oldpins = None
-        self.oldclk = None
+        self.oldpins = self.oldclk = self.oldload = self.oldldac = None
+        self.datapin = None
         self.bits = []
         self.ss_dac = self.es_dac = 0
         self.ss_gain = self.es_gain = 0
         self.ss_value = self.es_value = 0
+        self.dac_select = self.gain = self.dac_value = None
 
     def start(self, metadata):
         # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620')
@@ -70,17 +70,43 @@ class Decoder(srd.Decoder):
 
     def handle_11bits(self):
         s = "".join(str(i) for i in self.bits[:2])
+        self.dac_select = dacs[int(s, 2)]
         self.put(self.ss_dac, self.es_dac, self.out_ann,
-                 [0, ['DAC select: %s' % dacs[int(s, 2)]]])
+                 [0, ['DAC select: %s' % self.dac_select]])
 
+        self.gain = 1 + self.bits[2]
         self.put(self.ss_gain, self.es_gain, self.out_ann,
-                 [0, ['Gain: x%d' % (1 + self.bits[2])]])
+                 [0, ['Gain: x%d' % self.gain]])
 
         s = "".join(str(i) for i in self.bits[3:])
+        self.dac_value = int(s, 2)
         self.put(self.ss_value, self.es_value, self.out_ann,
-                 [0, ['DAC value: %d' % int(s, 2)]])
-
-        self.bits = []
+                 [0, ['DAC value: %d' % self.dac_value]])
+
+    def handle_falling_edge_load(self):
+        self.put(self.samplenum, self.samplenum, self.out_ann,
+                 [0, ['Setting %s value to %d (x%d gain)' % \
+                 (self.dac_select, self.dac_value, self.gain)]])
+
+    def handle_falling_edge_ldac(self):
+        self.put(self.samplenum, self.samplenum, self.out_ann,
+                 [0, ['Falling edge on LDAC pin']])
+
+    def handle_new_dac_bit(self):
+        self.bits.append(self.datapin)
+
+        # Wait until we have read 11 bits, then parse them.
+        l, s = len(self.bits), self.samplenum
+        if l == 1:
+            self.ss_dac = s
+        elif l == 2:
+            self.es_dac = self.ss_gain = s
+        elif l == 3:
+            self.es_gain = self.ss_value = s
+        elif l == 11:
+            self.es_value = s
+            self.handle_11bits()
+            self.bits = []
 
     def decode(self, ss, es, data):
         for (self.samplenum, pins) in data:
@@ -88,31 +114,19 @@ class Decoder(srd.Decoder):
             # Ignore identical samples early on (for performance reasons).
             if self.oldpins == pins:
                 continue
-            self.oldpins, (clk, data, load, ldac) = pins, pins
+            self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
 
             # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
-            # TODO: Handle various LOAD-/LDAC-controlled methods.
-            if not (self.oldclk == 1 and clk == 0):
-                self.oldclk = clk
-                continue
+            # A falling edge of LOAD will latch the data.
 
-            # The DAC has received a new bit, store it.
-            self.bits.append(data)
-
-            if self.state == 'IDLE':
-                # Wait until we have read 11 bits, then parse them.
-                l, s = len(self.bits), self.samplenum
-                if l == 1:
-                    self.ss_dac = s
-                elif l == 2:
-                    self.es_dac = self.ss_gain = s
-                elif l == 3:
-                    self.es_gain = self.ss_value = s
-                elif l == 11:
-                    self.es_value = s
-                    self.handle_11bits()
-            else:
-                raise Exception('Invalid state: %s' % self.state)
+            if self.oldload == 1 and load == 0:
+                self.handle_falling_edge_load()
+            if self.oldldac == 1 and ldac == 0:
+                self.handle_falling_edge_ldac()
+            if self.oldclk == 1 and clk == 0:
+                self.handle_new_dac_bit()
 
             self.oldclk = clk
+            self.oldload = load
+            self.oldldac = ldac