- # We received 8 address/data bits and the ACK/NACK bit.
- data >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
- d = (state == ADDRESS) and (data & 0xfe) or data
- if state == ADDRESS:
- wr = (data & 1) and 1 or 0
- state = DATA
- o = {'type': state,
- 'range': (startsample, samplenum - 1),
- 'data': d, 'ann': None}
- if state == ADDRESS and wr == 1:
- o['type'] = 'AW'
- elif state == ADDRESS and wr == 0:
- o['type'] = 'AR'
- elif state == DATA and wr == 1:
- o['type'] = 'DW'
- elif state == DATA and wr == 0:
- o['type'] = 'DR'
- out.append(o)
- o = {'type': ack, 'range': (samplenum, samplenum),
- 'data': None, 'ann': None}
- out.append(o)
- bitcount = data = startsample = 0
- startsample = -1
-
- # STOP condition (P): SDA = rising, SCL = high
- elif (oldsda == 0 and sda == 1) and scl == 1:
- o = {'type': 'P', 'range': (samplenum, samplenum),
- 'data': None, 'ann': None},
- out.append(o)
- state = IDLE
- wr = -1
-
- # Save current SDA/SCL values for the next round.
- oldscl = scl
- oldsda = sda
-
- # FIXME: Just for testing...
- return str(out)
-
-register = {
- 'id': 'i2c',
- 'name': 'I2C',
- 'longname': 'Inter-Integrated Circuit (I2C) bus',
- 'desc': 'I2C is a two-wire, multi-master, serial bus.',
- 'longdesc': '...',
- 'author': 'Uwe Hermann',
- 'email': 'uwe@hermann-uwe.de',
- 'license': 'gplv2+',
- 'in': ['logic'],
- 'out': ['i2c'],
- 'probes': [
- ['scl', 'Serial clock line'],
- ['sda', 'Serial data line'],
- ],
- 'options': {
- 'address-space': ['Address space (in bits)', 7],
- },
- # 'start': start,
- # 'report': report,
-}
+ # Get SCL/SDA bit values (0/1 for low/high).
+ scl = (s & (1 << self.scl_bit)) >> self.scl_bit
+ sda = (s & (1 << self.sda_bit)) >> self.sda_bit
+
+ # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
+
+ # START condition (S): SDA = falling, SCL = high
+ if (self.oldsda == 1 and sda == 0) and scl == 1:
+ o = {'type': 'S', 'range': (self.samplenum, self.samplenum),
+ 'data': None, 'ann': None},
+ out.append(o)
+ self.state = self.ADDRESS
+ self.bitcount = self.databyte = 0
+
+ # Data latching by transmitter: SCL = low
+ elif (scl == 0):
+ pass # TODO
+
+ # Data sampling of receiver: SCL = rising
+ elif (self.oldscl == 0 and scl == 1):
+ if self.startsample == -1:
+ self.startsample = self.samplenum
+ self.bitcount += 1
+
+ # out.append("%d\t\tRECEIVED BIT %d: %d\n" % \
+ # (self.samplenum, 8 - bitcount, sda))
+
+ # Address and data are transmitted MSB-first.
+ self.databyte <<= 1
+ self.databyte |= sda
+
+ if self.bitcount != 9:
+ continue
+
+ # We received 8 address/data bits and the ACK/NACK bit.
+ self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
+ ack = (sda == 1) and 'N' or 'A'
+ d = (self.state == self.ADDRESS) and (self.databyte & 0xfe) or self.databyte
+ if self.state == self.ADDRESS:
+ self.wr = (self.databyte & 1) and 1 or 0
+ self.state = self.DATA
+ o = {'type': self.state,
+ 'range': (self.startsample, self.samplenum - 1),
+ 'data': d, 'ann': None}
+ if self.state == self.ADDRESS and self.wr == 1:
+ o['type'] = 'AW'
+ elif self.state == self.ADDRESS and self.wr == 0:
+ o['type'] = 'AR'
+ elif self.state == self.DATA and self.wr == 1:
+ o['type'] = 'DW'
+ elif self.state == self.DATA and self.wr == 0:
+ o['type'] = 'DR'
+ out.append(o)
+ o = {'type': ack, 'range': (self.samplenum, self.samplenum),
+ 'data': None, 'ann': None}
+ out.append(o)
+ self.bitcount = self.databyte = self.startsample = 0
+ self.startsample = -1
+
+ # STOP condition (P): SDA = rising, SCL = high
+ elif (self.oldsda == 0 and sda == 1) and scl == 1:
+ o = {'type': 'P', 'range': (self.samplenum, self.samplenum),
+ 'data': None, 'ann': None},
+ out.append(o)
+ self.state = self.IDLE
+ self.wr = -1
+
+ # Save current SDA/SCL values for the next round.
+ self.oldscl = scl
+ self.oldsda = sda
+
+ # TODO: Which output format?
+ # TODO: How to only output something after the last chunk of data?
+ if out != []:
+ sigrok.put(out)