- # DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
- # When transferring data IN:
- # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
- # Bits[2:1] = A[3:2]: 2-bit address of a debug port register
- # Bits[0:0] = RnW: Read request (1) or write request (0)
- # When transferring data OUT:
- # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
- # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
- def handle_reg_dpacc(self, bits):
- self.put(self.ss, self.es, self.out_ann, [0, ['DPACC: ' + bits]])
-
- # TODO: When to use Data IN / Data OUT?
- self.put(self.ss, self.es, self.out_ann, [0, [dpacc_data_in(bits)]])
- self.put(self.ss, self.es, self.out_ann, [0, [dpacc_data_out(bits)]])
-
- # APACC is used to access all Access Port (AHB-AP) registers.
- # When transferring data IN:
- # Bits[34:3] = DATA[31:0]: 32bit data to shift in (write request)
- # Bits[2:1] = A[3:2]: 2-bit address (sub-address AP register)
- # Bits[0:0] = RnW: Read request (1) or write request (0)
- # When transferring data OUT:
- # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
- # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
- def handle_reg_apacc(self, bits):
- self.put(self.ss, self.es, self.out_ann, [0, ['APACC: ' + bits]])
-
- # TODO: When to use Data IN / Data OUT?
- self.put(self.ss, self.es, self.out_ann, [0, [dpacc_data_in(bits)]])
- self.put(self.ss, self.es, self.out_ann, [0, [dpacc_data_out(bits)]])
-
- def handle_reg_abort(self, bits):
+ def handle_reg_dpacc(self, cmd, bits):
+ # self.put(self.ss, self.es, self.out_ann,
+ # [0, ['DPACC/%s: %s' % (cmd, bits)]])
+ s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
+ self.put(self.ss, self.es, self.out_ann, [0, [s]])
+
+ def handle_reg_apacc(self, cmd, bits):
+ # self.put(self.ss, self.es, self.out_ann,
+ # [0, ['APACC/%s: %s' % (cmd, bits)]])
+ s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
+ self.put(self.ss, self.es, self.out_ann, [0, [s]])
+
+ def handle_reg_abort(self, cmd, bits):