parallel: unify decode() code paths with and without clock signal
authorGerhard Sittig <gerhard.sittig@gmx.net>
Fri, 22 Dec 2017 12:55:45 +0000 (13:55 +0100)
committerUwe Hermann <uwe@hermann-uwe.de>
Mon, 1 Jan 2018 21:15:51 +0000 (22:15 +0100)
Instead of implementing two main loops for operation in the presence and
in the absence of a clock line, use a common main loop which operates on
pre-determined wait conditions.

decoders/parallel/pd.py

index 140b7b8b34a6f5f3eb697977d688a9f59c8bcfa6..4c09d86235e45b0d332511f91826ae59c364e191 100644 (file)
@@ -176,10 +176,11 @@ class Decoder(srd.Decoder):
             for i in range(1, len(self.optional_channels)):
                 if self.has_channel(i):
                     conds.append({i: 'e'})
-            while True:
-                self.handle_bits(self.wait(conds)[1:])
         else:
             # Sample on the rising or falling CLK edge (depends on config).
-            while True:
-                pins = self.wait({0: self.options['clock_edge'][0]})
-                self.handle_bits(pins[1:])
+            edge = self.options['clock_edge'][0]
+            conds = [{0: edge}]
+
+        while True:
+            pins = self.wait(conds)
+            self.handle_bits(pins[1:])