X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=bb4ef3d262b09b60bcca6617d86514b63ed20d5d;hp=28c36707b9a789d9bf4dcf5191960661e9079163;hb=8ad6e500312084cd4ae43c7bda476cc7370cda20;hpb=f38ec2855ce41154bc1035dd7f1ab9a21f411f0d diff --git a/type_logic.c b/type_logic.c index 28c3670..bb4ef3d 100644 --- a/type_logic.c +++ b/type_logic.c @@ -22,42 +22,42 @@ #include #include - -PyObject *srd_logic_iter(PyObject *self) +static PyObject *srd_logic_iter(PyObject *self) { - return self; } -PyObject *srd_logic_iternext(PyObject *self) +static PyObject *srd_logic_iternext(PyObject *self) { + int i; PyObject *py_samplenum, *py_samples; srd_logic *logic; uint64_t sample; - int i; unsigned char probe_samples[SRD_MAX_NUM_PROBES]; - logic = (srd_logic *) self; + logic = (srd_logic *)self; if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) { /* End iteration loop. */ return NULL; } - /* Convert the bit-packed sample to an array of bytes, with only 0x01 + /* + * Convert the bit-packed sample to an array of bytes, with only 0x01 * and 0x00 values, so the PD doesn't need to do any bitshifting. */ - memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize, - logic->di->data_unitsize); - for (i = 0; i < logic->di->dec_num_probes; i++) { - probe_samples[logic->di->dec_probemap[i]] = sample & 0x01; - sample >>= 1; - } + memcpy(&sample, + logic->inbuf + logic->itercnt * logic->di->data_unitsize, + logic->di->data_unitsize); + for (i = 0; i < logic->di->dec_num_probes; i++) + probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; /* Prepare the next samplenum/sample list in this iteration. */ - py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt); + py_samplenum = + PyLong_FromUnsignedLongLong(logic->start_samplenum + + logic->itercnt); PyList_SetItem(logic->sample, 0, py_samplenum); py_samples = PyBytes_FromStringAndSize((const char *)probe_samples, - logic->di->dec_num_probes); + logic->di->dec_num_probes); PyList_SetItem(logic->sample, 1, py_samples); Py_INCREF(logic->sample); logic->itercnt++; @@ -65,7 +65,7 @@ PyObject *srd_logic_iternext(PyObject *self) return logic->sample; } -PyTypeObject srd_logic_type = { +SRD_PRIV PyTypeObject srd_logic_type = { PyVarObject_HEAD_INIT(NULL, 0) .tp_name = "srd_logic", .tp_basicsize = sizeof(srd_logic), @@ -74,4 +74,3 @@ PyTypeObject srd_logic_type = { .tp_iter = srd_logic_iter, .tp_iternext = srd_logic_iternext, }; -