X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=ba356c0a9526246d953138275dd21aff4e9a4a04;hp=ded0062456467658f8645353c89e0a1671c30a93;hb=ba2eca6e2d52e6ebe342a50ebf7b0c00a55bdc55;hpb=57790bc8c558ccf2e57b3d973c043088232628c7 diff --git a/type_logic.c b/type_logic.c index ded0062..ba356c0 100644 --- a/type_logic.c +++ b/type_logic.c @@ -1,5 +1,5 @@ /* - * This file is part of the sigrok project. + * This file is part of the libsigrokdecode project. * * Copyright (C) 2012 Bert Vermeulen * @@ -17,8 +17,9 @@ * along with this program. If not, see . */ -#include "sigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */ -#include "config.h" +#include +#include "libsigrokdecode-internal.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */ +#include "libsigrokdecode.h" #include #include @@ -29,11 +30,10 @@ static PyObject *srd_logic_iter(PyObject *self) static PyObject *srd_logic_iternext(PyObject *self) { - int i; - PyObject *py_samplenum, *py_samples; srd_logic *logic; - uint64_t sample; - uint8_t probe_samples[SRD_MAX_NUM_PROBES + 1]; + PyObject *py_samplenum, *py_samples; + uint8_t *sample_pos, sample; + int byte_offset, bit_offset, i; logic = (srd_logic *)self; if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) { @@ -45,34 +45,27 @@ static PyObject *srd_logic_iternext(PyObject *self) * Convert the bit-packed sample to an array of bytes, with only 0x01 * and 0x00 values, so the PD doesn't need to do any bitshifting. */ - - /* Get probe bits into the 'sample' variable. */ - memcpy(&sample, - logic->inbuf + logic->itercnt * logic->di->data_unitsize, - logic->di->data_unitsize); - - /* All probe values (required + optional) are pre-set to 42. */ - memset(probe_samples, 42, logic->di->dec_num_probes); - /* TODO: None or -1 in Python would be better. */ - - /* - * Set probe values of specified/used probes to their resp. values. - * Unused probe values (those not specified by the user) remain at 42. - */ - for (i = 0; i < logic->di->dec_num_probes; i++) { - /* A probemap value of -1 means "unused optional probe". */ - if (logic->di->dec_probemap[i] == -1) - continue; - probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0; + sample_pos = logic->inbuf + logic->itercnt * logic->di->data_unitsize; + for (i = 0; i < logic->di->dec_num_channels; i++) { + /* A channelmap value of -1 means "unused optional channel". */ + if (logic->di->dec_channelmap[i] == -1) { + /* Value of unused channel is 0xff, instead of 0 or 1. */ + logic->di->channel_samples[i] = 0xff; + } else { + byte_offset = logic->di->dec_channelmap[i] / 8; + bit_offset = logic->di->dec_channelmap[i] % 8; + sample = *(sample_pos + byte_offset) & (1 << bit_offset) ? 1 : 0; + logic->di->channel_samples[i] = sample; + } } /* Prepare the next samplenum/sample list in this iteration. */ py_samplenum = - PyLong_FromUnsignedLongLong(logic->start_samplenum + + PyLong_FromUnsignedLongLong(logic->abs_start_samplenum + logic->itercnt); PyList_SetItem(logic->sample, 0, py_samplenum); - py_samples = PyBytes_FromStringAndSize((const char *)probe_samples, - logic->di->dec_num_probes); + py_samples = PyBytes_FromStringAndSize((const char *)logic->di->channel_samples, + logic->di->dec_num_channels); PyList_SetItem(logic->sample, 1, py_samples); Py_INCREF(logic->sample); logic->itercnt++; @@ -80,14 +73,25 @@ static PyObject *srd_logic_iternext(PyObject *self) return logic->sample; } -/** @cond PRIVATE */ -SRD_PRIV PyTypeObject srd_logic_type = { - PyVarObject_HEAD_INIT(NULL, 0) - .tp_name = "srd_logic", - .tp_basicsize = sizeof(srd_logic), - .tp_flags = Py_TPFLAGS_DEFAULT, - .tp_doc = "Sigrokdecode logic sample object", - .tp_iter = srd_logic_iter, - .tp_iternext = srd_logic_iternext, -}; -/** @endcond */ +/** Create the srd_logic type. + * @return The new type object. + * @private + */ +SRD_PRIV PyObject *srd_logic_type_new(void) +{ + PyType_Spec spec; + PyType_Slot slots[] = { + { Py_tp_doc, "sigrokdecode logic sample object" }, + { Py_tp_iter, (void *)&srd_logic_iter }, + { Py_tp_iternext, (void *)&srd_logic_iternext }, + { Py_tp_new, (void *)&PyType_GenericNew }, + { 0, NULL } + }; + spec.name = "srd_logic"; + spec.basicsize = sizeof(srd_logic); + spec.itemsize = 0; + spec.flags = Py_TPFLAGS_DEFAULT; + spec.slots = slots; + + return PyType_FromSpec(&spec); +}