X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=b284ebf73d09744215a72784a5567dd246b78235;hp=ebe81e33a6545abf210240735902feddf3a7235c;hb=322c6b2fb36aaa38967ca797acef0ebb1f3090e6;hpb=c9bfccc6347e05e6faba6f27fe0e50a7d55f531c

diff --git a/type_logic.c b/type_logic.c
index ebe81e3..b284ebf 100644
--- a/type_logic.c
+++ b/type_logic.c
@@ -22,18 +22,18 @@
 #include <inttypes.h>
 #include <string.h>
 
-PyObject *srd_logic_iter(PyObject *self)
+static PyObject *srd_logic_iter(PyObject *self)
 {
 	return self;
 }
 
-PyObject *srd_logic_iternext(PyObject *self)
+static PyObject *srd_logic_iternext(PyObject *self)
 {
 	int i;
 	PyObject *py_samplenum, *py_samples;
 	srd_logic *logic;
 	uint64_t sample;
-	unsigned char probe_samples[SRD_MAX_NUM_PROBES];
+	uint8_t probe_samples[SRD_MAX_NUM_PROBES + 1];
 
 	logic = (srd_logic *)self;
 	if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) {
@@ -49,8 +49,7 @@ PyObject *srd_logic_iternext(PyObject *self)
 	       logic->inbuf + logic->itercnt * logic->di->data_unitsize,
 	       logic->di->data_unitsize);
 	for (i = 0; i < logic->di->dec_num_probes; i++)
-		probe_samples[i] =
-		    sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
+		probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
 
 	/* Prepare the next samplenum/sample list in this iteration. */
 	py_samplenum =
@@ -66,7 +65,7 @@ PyObject *srd_logic_iternext(PyObject *self)
 	return logic->sample;
 }
 
-PyTypeObject srd_logic_type = {
+SRD_PRIV PyTypeObject srd_logic_type = {
 	PyVarObject_HEAD_INIT(NULL, 0)
 	.tp_name = "srd_logic",
 	.tp_basicsize = sizeof(srd_logic),