X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=9f2b39277570c7a920cb87b933b04888fefb5f0a;hp=b284ebf73d09744215a72784a5567dd246b78235;hb=3abc83b996547a69bad906ec748f30874aae4796;hpb=322c6b2fb36aaa38967ca797acef0ebb1f3090e6

diff --git a/type_logic.c b/type_logic.c
index b284ebf..9f2b392 100644
--- a/type_logic.c
+++ b/type_logic.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrokdecode project.
  *
  * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
  *
@@ -17,7 +17,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "sigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
+#include "libsigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
 #include "config.h"
 #include <inttypes.h>
 #include <string.h>
@@ -45,11 +45,26 @@ static PyObject *srd_logic_iternext(PyObject *self)
 	 * Convert the bit-packed sample to an array of bytes, with only 0x01
 	 * and 0x00 values, so the PD doesn't need to do any bitshifting.
 	 */
+
+	/* Get probe bits into the 'sample' variable. */
 	memcpy(&sample,
 	       logic->inbuf + logic->itercnt * logic->di->data_unitsize,
 	       logic->di->data_unitsize);
-	for (i = 0; i < logic->di->dec_num_probes; i++)
+
+	/* All probe values (required + optional) are pre-set to 42. */
+	memset(probe_samples, 42, logic->di->dec_num_probes);
+	/* TODO: None or -1 in Python would be better. */
+
+	/*
+	 * Set probe values of specified/used probes to their resp. values.
+	 * Unused probe values (those not specified by the user) remain at 42.
+	 */
+	for (i = 0; i < logic->di->dec_num_probes; i++) {
+		/* A probemap value of -1 means "unused optional probe". */
+		if (logic->di->dec_probemap[i] == -1)
+			continue;
 		probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
+	}
 
 	/* Prepare the next samplenum/sample list in this iteration. */
 	py_samplenum =
@@ -65,6 +80,7 @@ static PyObject *srd_logic_iternext(PyObject *self)
 	return logic->sample;
 }
 
+/** @cond PRIVATE */
 SRD_PRIV PyTypeObject srd_logic_type = {
 	PyVarObject_HEAD_INIT(NULL, 0)
 	.tp_name = "srd_logic",
@@ -74,3 +90,4 @@ SRD_PRIV PyTypeObject srd_logic_type = {
 	.tp_iter = srd_logic_iter,
 	.tp_iternext = srd_logic_iternext,
 };
+/** @endcond */