X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=80e49f163ed903014457057b975b037b50859b31;hp=2f7923425b08bae786db5e106bdc153864ae1584;hb=0169f19c53e195df2f96c4df731ad3214c59e20a;hpb=bc5f5a434e148db1843be7b02b95a35d21237702

diff --git a/type_logic.c b/type_logic.c
index 2f79234..80e49f1 100644
--- a/type_logic.c
+++ b/type_logic.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrokdecode project.
  *
  * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
  *
@@ -17,60 +17,71 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "sigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
+#include "libsigrokdecode.h" /* First, so we avoid a _POSIX_C_SOURCE warning. */
 #include "config.h"
 #include <inttypes.h>
 #include <string.h>
 
-
-PyObject *srd_logic_iter(PyObject *self)
+static PyObject *srd_logic_iter(PyObject *self)
 {
-
 	return self;
 }
 
-PyObject *srd_logic_iternext(PyObject *self)
+static PyObject *srd_logic_iternext(PyObject *self)
 {
-	PyObject *py_samplenum, *py_samples;
 	srd_logic *logic;
+	PyObject *py_samplenum, *py_samples;
 	uint64_t sample;
+	uint8_t probe_samples[SRD_MAX_NUM_PROBES + 1];
 	int i;
-	unsigned char probe_samples[SRD_MAX_NUM_PROBES];
 
-	logic = (srd_logic *) self;
-	if (logic->itercnt >= logic->inbuflen / logic->di->unitsize) {
+	logic = (srd_logic *)self;
+	if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) {
 		/* End iteration loop. */
 		return NULL;
 	}
 
-	/* TODO: use number of probes defined in the PD, in the order the PD
-	 * defined them -- not whatever came in from the driver.
-	 */
-	/* Convert the bit-packed sample to an array of bytes, with only 0x01
+	/*
+	 * Convert the bit-packed sample to an array of bytes, with only 0x01
 	 * and 0x00 values, so the PD doesn't need to do any bitshifting.
 	 */
-	memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->unitsize,
-			logic->di->unitsize);
-	for (i = 0; i < logic->di->num_probes; i++) {
-		probe_samples[i] = sample & 0x01;
-		sample >>= 1;
-	}
 
-	/* TODO: samplenum should be in the inbuf feed, instead of time/duration.
-	 * fake it for now...
+	/* Get probe bits into the 'sample' variable. */
+	memcpy(&sample,
+	       logic->inbuf + logic->itercnt * logic->di->data_unitsize,
+	       logic->di->data_unitsize);
+
+	/* All probe values (required + optional) are pre-set to 42. */
+	memset(probe_samples, 42, logic->di->dec_num_probes);
+	/* TODO: None or -1 in Python would be better. */
+
+	/*
+	 * Set probe values of specified/used probes to their resp. values.
+	 * Unused probe values (those not specified by the user) remain at 42.
 	 */
+	for (i = 0; i < logic->di->dec_num_probes; i++) {
+		/* A probemap value of -1 means "unused optional probe". */
+		if (logic->di->dec_probemap[i] == -1)
+			continue;
+		probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
+	}
+
 	/* Prepare the next samplenum/sample list in this iteration. */
-	py_samplenum = PyLong_FromUnsignedLongLong(logic->itercnt++);
+	py_samplenum =
+	    PyLong_FromUnsignedLongLong(logic->start_samplenum +
+					logic->itercnt);
 	PyList_SetItem(logic->sample, 0, py_samplenum);
 	py_samples = PyBytes_FromStringAndSize((const char *)probe_samples,
-			logic->di->num_probes);
+					       logic->di->dec_num_probes);
 	PyList_SetItem(logic->sample, 1, py_samples);
 	Py_INCREF(logic->sample);
+	logic->itercnt++;
 
 	return logic->sample;
 }
 
-PyTypeObject srd_logic_type = {
+/** @cond PRIVATE */
+SRD_PRIV PyTypeObject srd_logic_type = {
 	PyVarObject_HEAD_INIT(NULL, 0)
 	.tp_name = "srd_logic",
 	.tp_basicsize = sizeof(srd_logic),
@@ -79,4 +90,4 @@ PyTypeObject srd_logic_type = {
 	.tp_iter = srd_logic_iter,
 	.tp_iternext = srd_logic_iternext,
 };
-
+/** @endcond */