X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=7cea75bb4133c443274b133afed7c0eb25092144;hp=851a42ead51070334db360985b698962165df6be;hb=4244f8252706c5715a5598c51914f4f8d20c5e84;hpb=86528298fa2abfe825d6763b806095972e8bd8f4

diff --git a/type_logic.c b/type_logic.c
index 851a42e..7cea75b 100644
--- a/type_logic.c
+++ b/type_logic.c
@@ -38,29 +38,24 @@ PyObject *srd_logic_iternext(PyObject *self)
 	unsigned char probe_samples[SRD_MAX_NUM_PROBES];
 
 	logic = (srd_logic *) self;
-	if (logic->itercnt >= logic->inbuflen / logic->di->unitsize) {
+	if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) {
 		/* End iteration loop. */
 		return NULL;
 	}
 
-	/* TODO: use number of probes defined in the PD, in the order the PD
-	 * defined them -- not whatever came in from the driver.
-	 */
 	/* Convert the bit-packed sample to an array of bytes, with only 0x01
 	 * and 0x00 values, so the PD doesn't need to do any bitshifting.
 	 */
-	memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->unitsize,
-			logic->di->unitsize);
-	for (i = 0; i < logic->di->num_probes; i++) {
-		probe_samples[i] = sample & 0x01;
-		sample >>= 1;
-	}
+	memcpy(&sample, logic->inbuf + logic->itercnt * logic->di->data_unitsize,
+			logic->di->data_unitsize);
+	for (i = 0; i < logic->di->dec_num_probes; i++)
+		probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
 
 	/* Prepare the next samplenum/sample list in this iteration. */
 	py_samplenum = PyLong_FromUnsignedLongLong(logic->start_samplenum + logic->itercnt);
 	PyList_SetItem(logic->sample, 0, py_samplenum);
 	py_samples = PyBytes_FromStringAndSize((const char *)probe_samples,
-			logic->di->num_probes);
+			logic->di->dec_num_probes);
 	PyList_SetItem(logic->sample, 1, py_samples);
 	Py_INCREF(logic->sample);
 	logic->itercnt++;