X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=type_logic.c;h=6f266aa11110e0f39133f43c72c050530e0c6e53;hp=bb4ef3d262b09b60bcca6617d86514b63ed20d5d;hb=10b3851672d9047941079bca052751855f5ea5fa;hpb=582c8473ffd456dfb0796974ef2c0b1b78de38a8

diff --git a/type_logic.c b/type_logic.c
index bb4ef3d..6f266aa 100644
--- a/type_logic.c
+++ b/type_logic.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the libsigrokdecode project.
  *
  * Copyright (C) 2012 Bert Vermeulen <bert@biot.com>
  *
@@ -33,7 +33,7 @@ static PyObject *srd_logic_iternext(PyObject *self)
 	PyObject *py_samplenum, *py_samples;
 	srd_logic *logic;
 	uint64_t sample;
-	unsigned char probe_samples[SRD_MAX_NUM_PROBES];
+	uint8_t probe_samples[SRD_MAX_NUM_PROBES + 1];
 
 	logic = (srd_logic *)self;
 	if (logic->itercnt >= logic->inbuflen / logic->di->data_unitsize) {
@@ -45,11 +45,26 @@ static PyObject *srd_logic_iternext(PyObject *self)
 	 * Convert the bit-packed sample to an array of bytes, with only 0x01
 	 * and 0x00 values, so the PD doesn't need to do any bitshifting.
 	 */
+
+	/* Get probe bits into the 'sample' variable. */
 	memcpy(&sample,
 	       logic->inbuf + logic->itercnt * logic->di->data_unitsize,
 	       logic->di->data_unitsize);
-	for (i = 0; i < logic->di->dec_num_probes; i++)
+
+	/* All probe values (required + optional) are pre-set to 42. */
+	memset(probe_samples, 42, logic->di->dec_num_probes);
+	/* TODO: None or -1 in Python would be better. */
+
+	/*
+	 * Set probe values of specified/used probes to their resp. values.
+	 * Unused probe values (those not specified by the user) remain at 42.
+	 */
+	for (i = 0; i < logic->di->dec_num_probes; i++) {
+		/* A probemap value of -1 means "unused optional probe". */
+		if (logic->di->dec_probemap[i] == -1)
+			continue;
 		probe_samples[i] = sample & (1 << logic->di->dec_probemap[i]) ? 1 : 0;
+	}
 
 	/* Prepare the next samplenum/sample list in this iteration. */
 	py_samplenum =
@@ -65,6 +80,7 @@ static PyObject *srd_logic_iternext(PyObject *self)
 	return logic->sample;
 }
 
+/** @cond PRIVATE */
 SRD_PRIV PyTypeObject srd_logic_type = {
 	PyVarObject_HEAD_INIT(NULL, 0)
 	.tp_name = "srd_logic",
@@ -74,3 +90,4 @@ SRD_PRIV PyTypeObject srd_logic_type = {
 	.tp_iter = srd_logic_iter,
 	.tp_iternext = srd_logic_iternext,
 };
+/** @endcond */