X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=f07b76c931e6ad6ed28ca9d1d64b496ae9115ff8;hp=130b147de718711c737bf00c744a30f5836855c7;hb=da9bcbd9f45b0153465c55ec726a0d76f6d7f01e;hpb=d1e2129c7b01a760d48bcc8e7fc12956a62698c1

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index 130b147..f07b76c 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -72,32 +72,36 @@ class Decoder(srd.Decoder):
     license  = 'gplv2+'
     inputs   = ['logic']
     outputs  = ['z80']
-    probes = [
-        {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data bus line %d' % i}
-            for i in range(8)
-    ] + [
+    probes = tuple({
+            'id': 'd%d' % i,
+            'name': 'D%d' % i,
+            'desc': 'Data bus line %d' % i
+            } for i in range(8)
+    ) + (
         {'id': 'm1', 'name': '/M1', 'desc': 'Machine cycle 1'},
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
-    ]
-    optional_probes = [
+    )
+    optional_probes = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
-    ] + [
-        {'id': 'a%d' % i, 'name': 'A%d' % i, 'desc': 'Address bus line %d' % i}
-            for i in range(16)
-    ]
-    annotations = [
-        ['addr',  'Memory or I/O address'],
-        ['memrd', 'Byte read from memory'],
-        ['memwr', 'Byte written to memory'],
-        ['iord',  'Byte read from I/O port'],
-        ['iowr',  'Byte written to I/O port'],
-        ['instr', 'Z80 CPU instruction'],
-        ['rop',   'Value of input operand'],
-        ['wop',   'Value of output operand'],
-        ['warn',  'Warning message'],
-    ]
+    ) + tuple({
+        'id': 'a%d' % i,
+        'name': 'A%d' % i,
+        'desc': 'Address bus line %d' % i
+        } for i in range(16)
+    )
+    annotations = (
+        ('addr',  'Memory or I/O address'),
+        ('memrd', 'Byte read from memory'),
+        ('memwr', 'Byte written to memory'),
+        ('iord',  'Byte read from I/O port'),
+        ('iowr',  'Byte written to I/O port'),
+        ('instr', 'Z80 CPU instruction'),
+        ('rop',   'Value of input operand'),
+        ('wop',   'Value of output operand'),
+        ('warn',  'Warning message'),
+    )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),
         ('databus', 'Data bus', (Ann.MEMRD, Ann.MEMWR, Ann.IORD, Ann.IOWR)),