X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=cdbebebf27e2c2f0ceb8e02beab7afc5f00d538b;hp=f07b76c931e6ad6ed28ca9d1d64b496ae9115ff8;hb=HEAD;hpb=da9bcbd9f45b0153465c55ec726a0d76f6d7f01e

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index f07b76c..cdbebeb 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -56,7 +56,7 @@ ann_data_cycle_map = {
 
 def reduce_bus(bus):
     if 0xFF in bus:
-        return None # unassigned bus probes
+        return None # unassigned bus channels
     else:
         return reduce(lambda a, b: (a << 1) | b, reversed(bus))
 
@@ -64,15 +64,16 @@ def signed_byte(byte):
     return byte if byte < 128 else byte - 256
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id       = 'z80'
     name     = 'Z80'
     longname = 'Zilog Z80 CPU'
     desc     = 'Zilog Z80 microprocessor disassembly.'
-    license  = 'gplv2+'
+    license  = 'gplv3+'
     inputs   = ['logic']
-    outputs  = ['z80']
-    probes = tuple({
+    outputs  = []
+    tags     = ['Retro computing']
+    channels = tuple({
             'id': 'd%d' % i,
             'name': 'D%d' % i,
             'desc': 'Data bus line %d' % i
@@ -82,7 +83,7 @@ class Decoder(srd.Decoder):
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
     ) + tuple({
@@ -92,15 +93,15 @@ class Decoder(srd.Decoder):
         } for i in range(16)
     )
     annotations = (
-        ('addr',  'Memory or I/O address'),
+        ('addr', 'Memory or I/O address'),
         ('memrd', 'Byte read from memory'),
         ('memwr', 'Byte written to memory'),
-        ('iord',  'Byte read from I/O port'),
-        ('iowr',  'Byte written to I/O port'),
+        ('iord', 'Byte read from I/O port'),
+        ('iowr', 'Byte written to I/O port'),
         ('instr', 'Z80 CPU instruction'),
-        ('rop',   'Value of input operand'),
-        ('wop',   'Value of output operand'),
-        ('warn',  'Warning message'),
+        ('rop', 'Value of input operand'),
+        ('wop', 'Value of output operand'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),
@@ -110,7 +111,10 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (Ann.WARN,))
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.prev_cycle = Cycle.NONE
         self.op_state   = self.state_IDLE
 
@@ -129,8 +133,10 @@ class Decoder(srd.Decoder):
         self.op_state   = self.state_IDLE
         self.instr_len  = 0
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
+    def decode(self):
+        while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
+            pins = self.wait()
             cycle = Cycle.NONE
             if pins[Pin.MREQ] != 1: # default to asserted
                 if pins[Pin.RD] == 0: