X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=cdbebebf27e2c2f0ceb8e02beab7afc5f00d538b;hp=a8acf53c3aab2e327d544a7c4a765d7504db1afb;hb=HEAD;hpb=92b7b49f6964f57a7d6fc4473645c993cfa4ba52 diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py index a8acf53..cdbebeb 100644 --- a/decoders/z80/pd.py +++ b/decoders/z80/pd.py @@ -64,14 +64,15 @@ def signed_byte(byte): return byte if byte < 128 else byte - 256 class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'z80' name = 'Z80' longname = 'Zilog Z80 CPU' desc = 'Zilog Z80 microprocessor disassembly.' license = 'gplv3+' inputs = ['logic'] - outputs = ['z80'] + outputs = [] + tags = ['Retro computing'] channels = tuple({ 'id': 'd%d' % i, 'name': 'D%d' % i, @@ -92,15 +93,15 @@ class Decoder(srd.Decoder): } for i in range(16) ) annotations = ( - ('addr', 'Memory or I/O address'), + ('addr', 'Memory or I/O address'), ('memrd', 'Byte read from memory'), ('memwr', 'Byte written to memory'), - ('iord', 'Byte read from I/O port'), - ('iowr', 'Byte written to I/O port'), + ('iord', 'Byte read from I/O port'), + ('iowr', 'Byte written to I/O port'), ('instr', 'Z80 CPU instruction'), - ('rop', 'Value of input operand'), - ('wop', 'Value of output operand'), - ('warn', 'Warning message'), + ('rop', 'Value of input operand'), + ('wop', 'Value of output operand'), + ('warning', 'Warning'), ) annotation_rows = ( ('addrbus', 'Address bus', (Ann.ADDR,)), @@ -111,6 +112,9 @@ class Decoder(srd.Decoder): ) def __init__(self): + self.reset() + + def reset(self): self.prev_cycle = Cycle.NONE self.op_state = self.state_IDLE @@ -129,8 +133,10 @@ class Decoder(srd.Decoder): self.op_state = self.state_IDLE self.instr_len = 0 - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: + def decode(self): + while True: + # TODO: Come up with more appropriate self.wait() conditions. + pins = self.wait() cycle = Cycle.NONE if pins[Pin.MREQ] != 1: # default to asserted if pins[Pin.RD] == 0: