X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;h=b7ff9a56b16ac83cc62bba2e6781876241b306dc;hp=130b147de718711c737bf00c744a30f5836855c7;hb=10aeb8ea8b183394cebc0033f048f49f4262b57d;hpb=780770f1295b7fdeb4481eb42623bad5da1e19a7

diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py
index 130b147..b7ff9a5 100644
--- a/decoders/z80/pd.py
+++ b/decoders/z80/pd.py
@@ -56,7 +56,7 @@ ann_data_cycle_map = {
 
 def reduce_bus(bus):
     if 0xFF in bus:
-        return None # unassigned bus probes
+        return None # unassigned bus channels
     else:
         return reduce(lambda a, b: (a << 1) | b, reversed(bus))
 
@@ -64,40 +64,44 @@ def signed_byte(byte):
     return byte if byte < 128 else byte - 256
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 3
     id       = 'z80'
     name     = 'Z80'
     longname = 'Zilog Z80 CPU'
     desc     = 'Zilog Z80 microprocessor disassembly.'
-    license  = 'gplv2+'
+    license  = 'gplv3+'
     inputs   = ['logic']
     outputs  = ['z80']
-    probes = [
-        {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data bus line %d' % i}
-            for i in range(8)
-    ] + [
+    channels = tuple({
+            'id': 'd%d' % i,
+            'name': 'D%d' % i,
+            'desc': 'Data bus line %d' % i
+            } for i in range(8)
+    ) + (
         {'id': 'm1', 'name': '/M1', 'desc': 'Machine cycle 1'},
         {'id': 'rd', 'name': '/RD', 'desc': 'Memory or I/O read'},
         {'id': 'wr', 'name': '/WR', 'desc': 'Memory or I/O write'},
-    ]
-    optional_probes = [
+    )
+    optional_channels = (
         {'id': 'mreq', 'name': '/MREQ', 'desc': 'Memory request'},
         {'id': 'iorq', 'name': '/IORQ', 'desc': 'I/O request'},
-    ] + [
-        {'id': 'a%d' % i, 'name': 'A%d' % i, 'desc': 'Address bus line %d' % i}
-            for i in range(16)
-    ]
-    annotations = [
-        ['addr',  'Memory or I/O address'],
-        ['memrd', 'Byte read from memory'],
-        ['memwr', 'Byte written to memory'],
-        ['iord',  'Byte read from I/O port'],
-        ['iowr',  'Byte written to I/O port'],
-        ['instr', 'Z80 CPU instruction'],
-        ['rop',   'Value of input operand'],
-        ['wop',   'Value of output operand'],
-        ['warn',  'Warning message'],
-    ]
+    ) + tuple({
+        'id': 'a%d' % i,
+        'name': 'A%d' % i,
+        'desc': 'Address bus line %d' % i
+        } for i in range(16)
+    )
+    annotations = (
+        ('addr',  'Memory or I/O address'),
+        ('memrd', 'Byte read from memory'),
+        ('memwr', 'Byte written to memory'),
+        ('iord',  'Byte read from I/O port'),
+        ('iowr',  'Byte written to I/O port'),
+        ('instr', 'Z80 CPU instruction'),
+        ('rop',   'Value of input operand'),
+        ('wop',   'Value of output operand'),
+        ('warn',  'Warning message'),
+    )
     annotation_rows = (
         ('addrbus', 'Address bus', (Ann.ADDR,)),
         ('databus', 'Data bus', (Ann.MEMRD, Ann.MEMWR, Ann.IORD, Ann.IOWR)),
@@ -106,7 +110,10 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (Ann.WARN,))
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.prev_cycle = Cycle.NONE
         self.op_state   = self.state_IDLE
 
@@ -125,8 +132,10 @@ class Decoder(srd.Decoder):
         self.op_state   = self.state_IDLE
         self.instr_len  = 0
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, pins) in data:
+    def decode(self):
+        while True:
+            # TODO: Come up with more appropriate self.wait() conditions.
+            pins = self.wait()
             cycle = Cycle.NONE
             if pins[Pin.MREQ] != 1: # default to asserted
                 if pins[Pin.RD] == 0: