X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fz80%2Fpd.py;fp=decoders%2Fz80%2Fpd.py;h=60c672f5e17ed52f0b146d28cfd5b7410cfc0b93;hp=c88ea059bbaa41c63ed41efe87cc4a5fb87e8624;hb=e029ab1f6ff7fc8e06a4869417a875136318515f;hpb=8830db5df55241e1ea775a70671ecb11235cf3c1 diff --git a/decoders/z80/pd.py b/decoders/z80/pd.py index c88ea05..60c672f 100644 --- a/decoders/z80/pd.py +++ b/decoders/z80/pd.py @@ -80,13 +80,13 @@ def signed_byte(byte): class Decoder(srd.Decoder): api_version = 1 - id = 'z80' - name = 'Z80' - longname = 'Zilog Z80 CPU' - desc = 'Zilog Z80 microprocessor disassembly.' - license = 'gplv2+' - inputs = ['logic'] - outputs = ['z80'] + id = 'z80' + name = 'Z80' + longname = 'Zilog Z80 CPU' + desc = 'Zilog Z80 microprocessor disassembly.' + license = 'gplv2+' + inputs = ['logic'] + outputs = ['z80'] probes = [ {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data bus line %d' % i} for i in range(8) @@ -104,15 +104,15 @@ class Decoder(srd.Decoder): ] options = {} annotations = [ - ['addr', 'Memory or I/O address'], - ['memrd', 'Byte read from memory'], - ['memwr', 'Byte written to memory'], - ['iord', 'Byte read from I/O port'], - ['iowr', 'Byte written to I/O port'], - ['instr', 'Z80 CPU instruction'], - ['rop', 'Value of input operand'], - ['wop', 'Value of output operand'], - ['warning', 'Warning message'], + ['addr', 'Memory or I/O address'], + ['memrd', 'Byte read from memory'], + ['memwr', 'Byte written to memory'], + ['iord', 'Byte read from I/O port'], + ['iowr', 'Byte written to I/O port'], + ['instr', 'Z80 CPU instruction'], + ['rop', 'Value of input operand'], + ['wop', 'Value of output operand'], + ['warn', 'Warning message'], ] annotation_rows = ( ('addrbus', 'Address bus', (Ann.ADDR,)),