X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=f039aa329426d3df02840eb53c4c94010d1816fe;hp=44aaaca1d8135d487788a90f9acd47edc28e5545;hb=6fbab493aaee26f9ecba0268261d1f3264339d9d;hpb=edad813467a4a248edaa1c91377d532b2e7f8786 diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index 44aaaca..f039aa3 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -19,10 +19,30 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# USB signalling (low-speed and full-speed) protocol decoder - import sigrokdecode as srd +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +, : + - 'SOP', None + - 'SYM', + - 'BIT', + - 'STUFF BIT', None + - 'EOP', None + - 'ERR', None + +: + - 'J', 'K', 'SE0', or 'SE1' + +: + - '0' or '1' + - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. +''' + # Low-/full-speed symbols. # Note: Low-speed J and K are inverted compared to the full-speed J and K! symbols = { @@ -47,8 +67,18 @@ bitrates = { 'full-speed': 12000000, # 12Mb/s (+/- 0.25%) } +sym_annotation = { + 'J': [0, ['J']], + 'K': [1, ['K']], + 'SE0': [2, ['SE0', '0']], + 'SE1': [3, ['SE1', '1']], +} + +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'usb_signalling' name = 'USB signalling' longname = 'Universal Serial Bus (LS/FS) signalling' @@ -56,85 +86,113 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['usb_signalling'] - probes = [ + channels = ( {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, - ] - optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } - annotations = [ - ['symbol', 'Symbol'], - ['sop', 'Start of packet (SOP)'], - ['eop', 'End of packet (EOP)'], - ['bit', 'Bit'], - ['stuffbit', 'Stuff bit'], - ['packet', 'Packet'], - ] + ) + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, + ) + annotations = ( + ('sym-j', 'J symbol'), + ('sym-k', 'K symbol'), + ('sym-se0', 'SE0 symbol'), + ('sym-se1', 'SE1 symbol'), + ('sop', 'Start of packet (SOP)'), + ('eop', 'End of packet (EOP)'), + ('bit', 'Bit'), + ('stuffbit', 'Stuff bit'), + ('error', 'Error'), + ) + annotation_rows = ( + ('bits', 'Bits', (4, 5, 6, 7, 8)), + ('symbols', 'Symbols', (0, 1, 2, 3)), + ) def __init__(self): + self.samplerate = None self.oldsym = 'J' # The "idle" state is J. - self.ss_sop = -1 + self.ss_block = None self.samplenum = 0 - self.packet = '' - self.syms = [] self.bitrate = None self.bitwidth = None - self.bitnum = 0 + self.samplepos = None self.samplenum_target = None + self.samplenum_edge = None + self.samplenum_lastedge = 0 self.oldpins = None + self.edgepins = None self.consecutive_ones = 0 self.state = 'IDLE' - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling') - self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling') - self.bitrate = bitrates[self.options['signalling']] - self.bitwidth = float(metadata['samplerate']) / float(self.bitrate) + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.bitrate = bitrates[self.options['signalling']] + self.bitwidth = float(self.samplerate) / float(self.bitrate) def putpx(self, data): - self.put(self.samplenum, self.samplenum, self.out_proto, data) + s = self.samplenum_edge + self.put(s, s, self.out_python, data) def putx(self, data): - self.put(self.samplenum, self.samplenum, self.out_ann, data) + s = self.samplenum_edge + self.put(s, s, self.out_ann, data) + + def putpm(self, data): + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_python, data) + + def putm(self, data): + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_ann, data) def putpb(self, data): - s, halfbit = self.samplenum, int(self.bitwidth / 2) - self.put(s - halfbit, s + halfbit, self.out_proto, data) + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_python, data) def putb(self, data): - s, halfbit = self.samplenum, int(self.bitwidth / 2) - self.put(s - halfbit, s + halfbit, self.out_ann, data) + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_ann, data) def set_new_target_samplenum(self): - bitpos = self.ss_sop + (self.bitwidth / 2) - bitpos += self.bitnum * self.bitwidth - self.samplenum_target = int(bitpos) + self.samplepos += self.bitwidth; + self.samplenum_target = int(self.samplepos) + self.samplenum_lastedge = self.samplenum_edge + self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2)) def wait_for_sop(self, sym): # Wait for a Start of Packet (SOP), i.e. a J->K symbol change. if sym != 'K': self.oldsym = sym return - self.ss_sop = self.samplenum + self.consecutive_ones = 0 + self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5 self.set_new_target_samplenum() self.putpx(['SOP', None]) - self.putx([1, ['SOP']]) + self.putx([4, ['SOP', 'S']]) self.state = 'GET BIT' - def handle_bit(self, sym, b): - if self.consecutive_ones == 6 and b == '0': - # Stuff bit. Don't add to the packet, reset self.consecutive_ones. - self.putb([4, ['SB: %s/%s' % (sym, b)]]) - self.consecutive_ones = 0 + def handle_bit(self, b): + if self.consecutive_ones == 6: + if b == '0': + # Stuff bit. + self.putpb(['STUFF BIT', None]) + self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']]) + self.consecutive_ones = 0 + else: + self.putpb(['ERR', None]) + self.putb([8, ['Bit stuff error', 'BS ERR', 'B']]) + self.state = 'IDLE' else: - # Normal bit. Add it to the packet, update self.consecutive_ones. - self.putb([3, ['%s/%s' % (sym, b)]]) - self.packet += b + # Normal bit (not a stuff bit). + self.putpb(['BIT', b]) + self.putb([6, ['%s' % b]]) if b == '1': self.consecutive_ones += 1 else: @@ -142,34 +200,48 @@ class Decoder(srd.Decoder): def get_eop(self, sym): # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J. - self.syms.append(sym) - self.putpb(['SYM', sym]) - self.putb([0, ['%s' % sym]]) - self.bitnum += 1 self.set_new_target_samplenum() + self.putpb(['SYM', sym]) + self.putb(sym_annotation[sym]) self.oldsym = sym - if self.syms[-2:] == ['SE0', 'J']: - # Got an EOP, i.e. we now have a full packet. - self.putpb(['PACKET', self.packet]) - self.putb([5, ['PACKET: %s' % self.packet]]) - self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE' - self.consecutive_ones = 0 + if sym == 'SE0': + pass + elif sym == 'J': + # Got an EOP. + self.putpm(['EOP', None]) + self.putm([5, ['EOP', 'E']]) + self.state = 'IDLE' + self.bitwidth = float(self.samplerate) / float(self.bitrate) + else: + self.putpm(['ERR', None]) + self.putm([8, ['EOP Error', 'EErr', 'E']]) + self.state = 'IDLE' def get_bit(self, sym): + self.set_new_target_samplenum() if sym == 'SE0': - # Start of an EOP. Change state, run get_eop() for this bit. + # Start of an EOP. Change state, save edge self.state = 'GET EOP' - self.get_eop(sym) - return - self.syms.append(sym) + self.ss_block = self.samplenum_lastedge + else: + b = '0' if self.oldsym != sym else '1' + self.handle_bit(b) self.putpb(['SYM', sym]) - b = '0' if self.oldsym != sym else '1' - self.handle_bit(sym, b) - self.bitnum += 1 - self.set_new_target_samplenum() + self.putb(sym_annotation[sym]) + if self.oldsym != sym: + edgesym = symbols[self.options['signalling']][tuple(self.edgepins)] + if edgesym not in ('SE0', 'SE1'): + if edgesym == sym: + self.bitwidth = self.bitwidth - (0.001 * self.bitwidth) + self.samplepos = self.samplepos - (0.01 * self.bitwidth) + else: + self.bitwidth = self.bitwidth + (0.001 * self.bitwidth) + self.samplepos = self.samplepos + (0.01 * self.bitwidth) self.oldsym = sym def decode(self, ss, es, data): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') for (self.samplenum, pins) in data: # State machine. if self.state == 'IDLE': @@ -179,8 +251,11 @@ class Decoder(srd.Decoder): self.oldpins = pins sym = symbols[self.options['signalling']][tuple(pins)] self.wait_for_sop(sym) + self.edgepins = pins elif self.state in ('GET BIT', 'GET EOP'): # Wait until we're in the middle of the desired bit. + if self.samplenum == self.samplenum_edge: + self.edgepins = pins if self.samplenum < self.samplenum_target: continue sym = symbols[self.options['signalling']][tuple(pins)] @@ -188,6 +263,3 @@ class Decoder(srd.Decoder): self.get_bit(sym) elif self.state == 'GET EOP': self.get_eop(sym) - else: - raise Exception('Invalid state: %s' % self.state) -