X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=deecf1a84b9a55bbea3749a5dbcd077fc975441e;hp=0d21d2226405a0814f32ebde93f6a5b479e9554a;hb=85c03d6009c4939786925d9c9f8880f34f1b7eb7;hpb=f2a5df42ea41e6c4370d4efa1a27ab942ba1ddff

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 0d21d22..deecf1a 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -19,12 +19,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# USB signalling (low-speed and full-speed) protocol decoder
-
 import sigrokdecode as srd
 
 '''
-Protocol output format:
+OUTPUT_PYTHON format:
 
 Packet:
 [<ptype>, <pdata>]
@@ -68,6 +66,13 @@ bitrates = {
     'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
 }
 
+sym_idx = {
+    'J': 0,
+    'K': 1,
+    'SE0': 2,
+    'SE1': 3,
+}
+
 class Decoder(srd.Decoder):
     api_version = 1
     id = 'usb_signalling'
@@ -77,21 +82,28 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb_signalling']
-    probes = [
+    probes = (
         {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
-    ]
-    optional_probes = []
-    options = {
-        'signalling': ['Signalling', 'full-speed'],
-    }
-    annotations = [
-        ['sym', 'Symbol'],
-        ['sop', 'Start of packet (SOP)'],
-        ['eop', 'End of packet (EOP)'],
-        ['bit', 'Bit'],
-        ['stuffbit', 'Stuff bit'],
-    ]
+    )
+    options = (
+        {'id': 'signalling', 'desc': 'Signalling',
+            'default': 'full-speed', 'values': ('full-speed', 'low-speed')},
+    )
+    annotations = (
+        ('sym-j', 'J symbol'),
+        ('sym-k', 'K symbol'),
+        ('sym-se0', 'SE0 symbol'),
+        ('sym-se1', 'SE1 symbol'),
+        ('sop', 'Start of packet (SOP)'),
+        ('eop', 'End of packet (EOP)'),
+        ('bit', 'Bit'),
+        ('stuffbit', 'Stuff bit'),
+    )
+    annotation_rows = (
+        ('bits', 'Bits', (4, 5, 6, 7)),
+        ('symbols', 'Symbols', (0, 1, 2, 3)),
+    )
 
     def __init__(self):
         self.samplerate = None
@@ -109,8 +121,8 @@ class Decoder(srd.Decoder):
         self.state = 'IDLE'
 
     def start(self):
-        self.out_proto = self.add(srd.OUTPUT_PYTHON, 'usb_signalling')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
+        self.out_python = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def metadata(self, key, value):
         if key == srd.SRD_CONF_SAMPLERATE:
@@ -119,18 +131,15 @@ class Decoder(srd.Decoder):
             self.bitwidth = float(self.samplerate) / float(self.bitrate)
             self.halfbit = int(self.bitwidth / 2)
 
-    def report(self):
-        pass
-
     def putpx(self, data):
-        self.put(self.samplenum, self.samplenum, self.out_proto, data)
+        self.put(self.samplenum, self.samplenum, self.out_python, data)
 
     def putx(self, data):
         self.put(self.samplenum, self.samplenum, self.out_ann, data)
 
     def putpm(self, data):
         s, h = self.samplenum, self.halfbit
-        self.put(self.ss_block - h, s + h, self.out_proto, data)
+        self.put(self.ss_block - h, s + h, self.out_python, data)
 
     def putm(self, data):
         s, h = self.samplenum, self.halfbit
@@ -138,7 +147,7 @@ class Decoder(srd.Decoder):
 
     def putpb(self, data):
         s, h = self.samplenum, self.halfbit
-        self.put(s - h, s + h, self.out_proto, data)
+        self.put(s - h, s + h, self.out_python, data)
 
     def putb(self, data):
         s, h = self.samplenum, self.halfbit
@@ -157,19 +166,21 @@ class Decoder(srd.Decoder):
         self.ss_sop = self.samplenum
         self.set_new_target_samplenum()
         self.putpx(['SOP', None])
-        self.putx([1, ['SOP']])
+        self.putx([4, ['SOP', 'S']])
         self.state = 'GET BIT'
 
     def handle_bit(self, sym, b):
         if self.consecutive_ones == 6 and b == '0':
             # Stuff bit.
             self.putpb(['STUFF BIT', None])
-            self.putb([4, ['SB: %s/%s' % (sym, b)]])
+            self.putb([7, ['Stuff bit: %s' % b, 'SB: %s' % b, '%s' % b]])
+            self.putb([sym_idx[sym], ['%s' % sym]])
             self.consecutive_ones = 0
         else:
             # Normal bit (not a stuff bit).
             self.putpb(['BIT', b])
-            self.putb([3, ['%s/%s' % (sym, b)]])
+            self.putb([6, ['%s' % b]])
+            self.putb([sym_idx[sym], ['%s' % sym]])
             if b == '1':
                 self.consecutive_ones += 1
             else:
@@ -179,14 +190,14 @@ class Decoder(srd.Decoder):
         # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
         self.syms.append(sym)
         self.putpb(['SYM', sym])
-        self.putb([0, ['%s' % sym]])
+        self.putb([sym_idx[sym], ['%s' % sym, '%s' % sym[0]]])
         self.bitnum += 1
         self.set_new_target_samplenum()
         self.oldsym = sym
         if self.syms[-2:] == ['SE0', 'J']:
             # Got an EOP.
             self.putpm(['EOP', None])
-            self.putm([2, ['EOP']])
+            self.putm([5, ['EOP', 'E']])
             self.bitnum, self.syms, self.state = 0, [], 'IDLE'
             self.consecutive_ones = 0