X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=8b98b7e6233686e94b6b369eca50d4cfe8a449b2;hp=df61628befe9d6eda851ffdc5c530e59e27736bc;hb=da9bcbd9f45b0153465c55ec726a0d76f6d7f01e;hpb=ab96960eded15c227208e49007a0b3f65c046aa3 diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index df61628..8b98b7e 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -19,10 +19,29 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# USB signalling (low-speed and full-speed) protocol decoder - import sigrokdecode as srd +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +, : + - 'SOP', None + - 'SYM', + - 'BIT', + - 'STUFF BIT', None + - 'EOP', None + +: + - 'J', 'K', 'SE0', or 'SE1' + +: + - 0 or 1 + - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. +''' + # Low-/full-speed symbols. # Note: Low-speed J and K are inverted compared to the full-speed J and K! symbols = { @@ -56,29 +75,32 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['usb_signalling'] - probes = [ + probes = ( {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, - ] - optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } - annotations = [ - ['symbol', 'Symbol'], - ['sop', 'Start of packet (SOP)'], - ['eop', 'End of packet (EOP)'], - ['bit', 'Bit'], - ['stuffbit', 'Stuff bit'], - ['packet', 'Packet'], - ] + ) + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, + ) + annotations = ( + ('sym', 'Symbol'), + ('sop', 'Start of packet (SOP)'), + ('eop', 'End of packet (EOP)'), + ('bit', 'Bit'), + ('stuffbit', 'Stuff bit'), + ) + annotation_rows = ( + ('bits', 'Bits', (1, 2, 3, 4)), + ('symbols', 'Symbols', (0,)), + ) def __init__(self): + self.samplerate = None self.oldsym = 'J' # The "idle" state is J. self.ss_sop = None self.ss_block = None self.samplenum = 0 - self.packet = '' self.syms = [] self.bitrate = None self.bitwidth = None @@ -88,33 +110,34 @@ class Decoder(srd.Decoder): self.consecutive_ones = 0 self.state = 'IDLE' - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling') - self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling') - self.bitrate = bitrates[self.options['signalling']] - self.bitwidth = float(metadata['samplerate']) / float(self.bitrate) - self.halfbit = int(self.bitwidth / 2) + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.bitrate = bitrates[self.options['signalling']] + self.bitwidth = float(self.samplerate) / float(self.bitrate) + self.halfbit = int(self.bitwidth / 2) def putpx(self, data): - self.put(self.samplenum, self.samplenum, self.out_proto, data) + self.put(self.samplenum, self.samplenum, self.out_python, data) def putx(self, data): self.put(self.samplenum, self.samplenum, self.out_ann, data) def putpm(self, data): s, h = self.samplenum, self.halfbit - self.put(self.ss_block - h, self.samplenum + h, self.out_proto, data) + self.put(self.ss_block - h, s + h, self.out_python, data) def putm(self, data): s, h = self.samplenum, self.halfbit - self.put(self.ss_block - h, self.samplenum + h, self.out_ann, data) + self.put(self.ss_block - h, s + h, self.out_ann, data) def putpb(self, data): s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_proto, data) + self.put(s - h, s + h, self.out_python, data) def putb(self, data): s, h = self.samplenum, self.halfbit @@ -138,13 +161,16 @@ class Decoder(srd.Decoder): def handle_bit(self, sym, b): if self.consecutive_ones == 6 and b == '0': - # Stuff bit. Don't add to the packet, reset self.consecutive_ones. - self.putb([4, ['SB: %s/%s' % (sym, b)]]) + # Stuff bit. + self.putpb(['STUFF BIT', None]) + self.putb([4, ['SB: %s' % b]]) + self.putb([0, ['%s' % sym]]) self.consecutive_ones = 0 else: - # Normal bit. Add it to the packet, update self.consecutive_ones. - self.putb([3, ['%s/%s' % (sym, b)]]) - self.packet += b + # Normal bit (not a stuff bit). + self.putpb(['BIT', b]) + self.putb([3, ['%s' % b]]) + self.putb([0, ['%s' % sym]]) if b == '1': self.consecutive_ones += 1 else: @@ -159,13 +185,10 @@ class Decoder(srd.Decoder): self.set_new_target_samplenum() self.oldsym = sym if self.syms[-2:] == ['SE0', 'J']: - # Got an EOP, i.e. we now have a full packet. + # Got an EOP. self.putpm(['EOP', None]) self.putm([2, ['EOP']]) - self.ss_block = self.ss_sop - self.putpm(['PACKET', self.packet]) - self.putm([5, ['PACKET: %s' % self.packet]]) - self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE' + self.bitnum, self.syms, self.state = 0, [], 'IDLE' self.consecutive_ones = 0 def get_bit(self, sym): @@ -184,6 +207,8 @@ class Decoder(srd.Decoder): self.oldsym = sym def decode(self, ss, es, data): + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") for (self.samplenum, pins) in data: # State machine. if self.state == 'IDLE':