X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=7b1ce2f57174ba65efd642e6b43bb581d5b4b74b;hp=4bf74b6ddaab6b93b9f4dec619da2de35a85063b;hb=d6d8a8a440ea2a81e6ddde33d16bc84d01cdb432;hpb=7dc75721f38ce781db1b8d512d626024acf35b59
diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index 4bf74b6..7b1ce2f 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -15,15 +15,36 @@
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see .
##
-# USB signalling (low-speed and full-speed) protocol decoder
-
import sigrokdecode as srd
-# Low-/full-speed symbols (used as states of our state machine, too).
+'''
+OUTPUT_PYTHON format:
+
+Packet:
+[, ]
+
+, :
+ - 'SOP', None
+ - 'SYM',
+ - 'BIT',
+ - 'STUFF BIT', None
+ - 'EOP', None
+ - 'ERR', None
+ - 'KEEP ALIVE', None
+ - 'RESET', None
+
+:
+ - 'J', 'K', 'SE0', or 'SE1'
+
+:
+ - '0' or '1'
+ - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
+'''
+
+# Low-/full-speed symbols.
# Note: Low-speed J and K are inverted compared to the full-speed J and K!
symbols = {
'low-speed': {
@@ -40,15 +61,46 @@ symbols = {
(0, 1): 'K',
(1, 1): 'SE1',
},
+ 'automatic': {
+ # (, ):
+ (0, 0): 'SE0',
+ (1, 0): 'FS_J',
+ (0, 1): 'LS_J',
+ (1, 1): 'SE1',
+ },
+ # After a PREamble PID, the bus segment between Host and Hub uses LS
+ # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
+ # both upstream and downstream low-speed data, the hub is responsible for
+ # inverting the polarity of the data before transmitting to/from a
+ # low-speed port.").
+ 'low-speed-rp': {
+ # (, ):
+ (0, 0): 'SE0',
+ (1, 0): 'J',
+ (0, 1): 'K',
+ (1, 1): 'SE1',
+ },
}
bitrates = {
- 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
+ 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
+ 'automatic': None
}
+sym_annotation = {
+ 'J': [0, ['J']],
+ 'K': [1, ['K']],
+ 'SE0': [2, ['SE0', '0']],
+ 'SE1': [3, ['SE1', '1']],
+}
+
+class SamplerateError(Exception):
+ pass
+
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 3
id = 'usb_signalling'
name = 'USB signalling'
longname = 'Universal Serial Bus (LS/FS) signalling'
@@ -56,105 +108,239 @@ class Decoder(srd.Decoder):
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb_signalling']
- probes = [
+ tags = ['PC']
+ channels = (
{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
- ]
- optional_probes = []
- options = {
- 'signalling': ['Signalling', 'full-speed'],
- }
- annotations = [
- ['Text', 'Human-readable text']
- ]
+ )
+ options = (
+ {'id': 'signalling', 'desc': 'Signalling',
+ 'default': 'automatic', 'values': ('automatic', 'full-speed', 'low-speed')},
+ )
+ annotations = (
+ ('sym-j', 'J symbol'),
+ ('sym-k', 'K symbol'),
+ ('sym-se0', 'SE0 symbol'),
+ ('sym-se1', 'SE1 symbol'),
+ ('sop', 'Start of packet (SOP)'),
+ ('eop', 'End of packet (EOP)'),
+ ('bit', 'Bit'),
+ ('stuffbit', 'Stuff bit'),
+ ('error', 'Error'),
+ ('keep-alive', 'Low-speed keep-alive'),
+ ('reset', 'Reset'),
+ )
+ annotation_rows = (
+ ('bits', 'Bits', (4, 5, 6, 7, 8, 9, 10)),
+ ('symbols', 'Symbols', (0, 1, 2, 3)),
+ )
def __init__(self):
- self.sym = 'J' # The "idle" state is J.
+ self.reset()
+
+ def reset(self):
+ self.samplerate = None
+ self.oldsym = 'J' # The "idle" state is J.
+ self.ss_block = None
self.samplenum = 0
- self.scount = 0
- self.packet = ''
- self.syms = []
self.bitrate = None
self.bitwidth = None
- self.oldpins = None
+ self.samplepos = None
+ self.samplenum_target = None
+ self.samplenum_edge = None
+ self.samplenum_lastedge = 0
+ self.edgepins = None
+ self.consecutive_ones = 0
+ self.bits = None
+ self.state = 'IDLE'
- def start(self, metadata):
- self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
- self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
- self.bitrate = bitrates[self.options['signalling']]
- self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
+ def start(self):
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_ann = self.register(srd.OUTPUT_ANN)
- def report(self):
- pass
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+ self.signalling = self.options['signalling']
+ if self.signalling != 'automatic':
+ self.update_bitrate()
- def putp(self, data):
- self.put(self.samplenum, self.samplenum, self.out_proto, data)
+ def update_bitrate(self):
+ self.bitrate = bitrates[self.signalling]
+ self.bitwidth = float(self.samplerate) / float(self.bitrate)
- def putx(self, data):
- self.put(self.samplenum, self.samplenum, self.out_ann, data)
+ def putpx(self, data):
+ s = self.samplenum_edge
+ self.put(s, s, self.out_python, data)
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
+ def putx(self, data):
+ s = self.samplenum_edge
+ self.put(s, s, self.out_ann, data)
- # Note: self.samplenum is the absolute sample number, whereas
- # self.scount only counts the number of samples since the
- # last change in the D+/D- lines.
- self.scount += 1
+ def putpm(self, data):
+ e = self.samplenum_edge
+ self.put(self.ss_block, e, self.out_python, data)
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins, (dp, dm) = pins, pins
+ def putm(self, data):
+ e = self.samplenum_edge
+ self.put(self.ss_block, e, self.out_ann, data)
- sym = symbols[self.options['signalling']][dp, dm]
+ def putpb(self, data):
+ s, e = self.samplenum_lastedge, self.samplenum_edge
+ self.put(s, e, self.out_python, data)
- self.putx([0, [sym]])
- self.putp(['SYM', sym])
+ def putb(self, data):
+ s, e = self.samplenum_lastedge, self.samplenum_edge
+ self.put(s, e, self.out_ann, data)
- # Wait for a symbol change (i.e., change in D+/D- lines).
- if sym == self.sym:
- continue
+ def set_new_target_samplenum(self):
+ self.samplepos += self.bitwidth
+ self.samplenum_target = int(self.samplepos)
+ self.samplenum_lastedge = self.samplenum_edge
+ self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
- ## # Debug code:
- ## self.syms.append(sym + ' ')
- ## if len(self.syms) == 16:
- ## self.putx([0, [''.join(self.syms)]])
- ## self.syms = []
- # continue
+ def wait_for_sop(self, sym):
+ # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
+ if sym != 'K' or self.oldsym != 'J':
+ return
+ self.consecutive_ones = 0
+ self.bits = ''
+ self.update_bitrate()
+ self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
+ self.set_new_target_samplenum()
+ self.putpx(['SOP', None])
+ self.putx([4, ['SOP', 'S']])
+ self.state = 'GET BIT'
- # How many bits since the last transition?
- if self.packet != '' or self.sym != 'J':
- bitcount = int((self.scount - 1) / self.bitwidth)
+ def handle_bit(self, b):
+ if self.consecutive_ones == 6:
+ if b == '0':
+ # Stuff bit.
+ self.putpb(['STUFF BIT', None])
+ self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
+ self.consecutive_ones = 0
else:
- bitcount = 0
-
- if self.sym == 'SE0':
- if bitcount == 1:
- # End-Of-Packet (EOP)
- # self.putx([0, [packet_decode(self.packet), self.packet]])
- if self.packet != '': # FIXME?
- self.putx([0, ['PACKET: %s' % self.packet]])
- self.putp(['PACKET', self.packet])
+ self.putpb(['ERR', None])
+ self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
+ self.state = 'IDLE'
+ else:
+ # Normal bit (not a stuff bit).
+ self.putpb(['BIT', b])
+ self.putb([6, ['%s' % b]])
+ if b == '1':
+ self.consecutive_ones += 1
+ else:
+ self.consecutive_ones = 0
+
+ def get_eop(self, sym):
+ # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
+ self.set_new_target_samplenum()
+ self.putpb(['SYM', sym])
+ self.putb(sym_annotation[sym])
+ self.oldsym = sym
+ if sym == 'SE0':
+ pass
+ elif sym == 'J':
+ # Got an EOP.
+ self.putpm(['EOP', None])
+ self.putm([5, ['EOP', 'E']])
+ self.state = 'WAIT IDLE'
+ else:
+ self.putpm(['ERR', None])
+ self.putm([8, ['EOP Error', 'EErr', 'E']])
+ self.state = 'IDLE'
+
+ def get_bit(self, sym):
+ self.set_new_target_samplenum()
+ b = '0' if self.oldsym != sym else '1'
+ self.oldsym = sym
+ if sym == 'SE0':
+ # Start of an EOP. Change state, save edge
+ self.state = 'GET EOP'
+ self.ss_block = self.samplenum_lastedge
+ else:
+ self.handle_bit(b)
+ self.putpb(['SYM', sym])
+ self.putb(sym_annotation[sym])
+ if len(self.bits) <= 16:
+ self.bits += b
+ if len(self.bits) == 16 and self.bits == '0000000100111100':
+ # Sync and low-speed PREamble seen
+ self.putpx(['EOP', None])
+ self.state = 'IDLE'
+ self.signalling = 'low-speed-rp'
+ self.update_bitrate()
+ self.oldsym = 'J'
+ if b == '0':
+ edgesym = symbols[self.signalling][tuple(self.edgepins)]
+ if edgesym not in ('SE0', 'SE1'):
+ if edgesym == sym:
+ self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
+ self.samplepos = self.samplepos - (0.01 * self.bitwidth)
+ else:
+ self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
+ self.samplepos = self.samplepos + (0.01 * self.bitwidth)
+
+ def handle_idle(self, sym):
+ self.samplenum_edge = self.samplenum
+ se0_length = float(self.samplenum - self.samplenum_lastedge) / self.samplerate
+ if se0_length > 2.5e-6: # 2.5us
+ self.putpb(['RESET', None])
+ self.putb([10, ['Reset', 'Res', 'R']])
+ self.signalling = self.options['signalling']
+ elif se0_length > 1.2e-6 and self.signalling == 'low-speed':
+ self.putpb(['KEEP ALIVE', None])
+ self.putb([9, ['Keep-alive', 'KA', 'A']])
+
+ if sym == 'FS_J':
+ self.signalling = 'full-speed'
+ self.update_bitrate()
+ elif sym == 'LS_J':
+ self.signalling = 'low-speed'
+ self.update_bitrate()
+ self.oldsym = 'J'
+ self.state = 'IDLE'
+
+ def decode(self):
+ if not self.samplerate:
+ raise SamplerateError('Cannot decode without samplerate.')
+
+ # Seed internal state from the very first sample.
+ pins = self.wait()
+ sym = symbols[self.options['signalling']][pins]
+ self.handle_idle(sym)
+
+ while True:
+ # State machine.
+ if self.state == 'IDLE':
+ # Wait for any edge on either DP and/or DM.
+ pins = self.wait([{0: 'e'}, {1: 'e'}])
+ sym = symbols[self.signalling][pins]
+ if sym == 'SE0':
+ self.samplenum_lastedge = self.samplenum
+ self.state = 'WAIT IDLE'
else:
- # Longer than EOP, assume reset.
- self.putx([0, ['RESET']])
- self.putp(['RESET', None])
- # self.putx([0, [self.packet]])
- self.scount = 0
- self.sym = sym
- self.packet = ''
- continue
-
- # Add bits to the packet string.
- self.packet += '1' * bitcount
-
- # Handle bit stuffing.
- if bitcount < 6 and sym != 'SE0':
- self.packet += '0'
- elif bitcount > 6:
- self.putx([0, ['BIT STUFF ERROR']])
- self.putp(['BIT STUFF ERROR', None])
-
- self.scount = 0
- self.sym = sym
+ self.wait_for_sop(sym)
+ self.edgepins = pins
+ elif self.state in ('GET BIT', 'GET EOP'):
+ # Wait until we're in the middle of the desired bit.
+ self.edgepins = self.wait([{'skip': self.samplenum_edge - self.samplenum}])
+ pins = self.wait([{'skip': self.samplenum_target - self.samplenum}])
+ sym = symbols[self.signalling][pins]
+ if self.state == 'GET BIT':
+ self.get_bit(sym)
+ elif self.state == 'GET EOP':
+ self.get_eop(sym)
+ elif self.state == 'WAIT IDLE':
+ # Skip "all-low" input. Wait for high level on either DP or DM.
+ pins = self.wait()
+ while not pins[0] and not pins[1]:
+ pins = self.wait([{0: 'h'}, {1: 'h'}])
+ if self.samplenum - self.samplenum_lastedge > 1:
+ sym = symbols[self.options['signalling']][pins]
+ self.handle_idle(sym)
+ else:
+ sym = symbols[self.signalling][pins]
+ self.wait_for_sop(sym)
+ self.edgepins = pins