X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=6f3ceffca75e771f22653b095bff6eaf74b877e1;hp=44aaaca1d8135d487788a90f9acd47edc28e5545;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=edad813467a4a248edaa1c91377d532b2e7f8786 diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index 44aaaca..6f3ceff 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -19,10 +19,29 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# USB signalling (low-speed and full-speed) protocol decoder - import sigrokdecode as srd +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +, : + - 'SOP', None + - 'SYM', + - 'BIT', + - 'STUFF BIT', None + - 'EOP', None + +: + - 'J', 'K', 'SE0', or 'SE1' + +: + - 0 or 1 + - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. +''' + # Low-/full-speed symbols. # Note: Low-speed J and K are inverted compared to the full-speed J and K! symbols = { @@ -61,23 +80,28 @@ class Decoder(srd.Decoder): {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, ] optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, + ) annotations = [ - ['symbol', 'Symbol'], + ['sym', 'Symbol'], ['sop', 'Start of packet (SOP)'], ['eop', 'End of packet (EOP)'], ['bit', 'Bit'], ['stuffbit', 'Stuff bit'], - ['packet', 'Packet'], ] + annotation_rows = ( + ('bits', 'Bits', (1, 2, 3, 4)), + ('symbols', 'Symbols', (0,)), + ) def __init__(self): + self.samplerate = None self.oldsym = 'J' # The "idle" state is J. - self.ss_sop = -1 + self.ss_sop = None + self.ss_block = None self.samplenum = 0 - self.packet = '' self.syms = [] self.bitrate = None self.bitwidth = None @@ -87,28 +111,38 @@ class Decoder(srd.Decoder): self.consecutive_ones = 0 self.state = 'IDLE' - def start(self, metadata): - self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling') - self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling') - self.bitrate = bitrates[self.options['signalling']] - self.bitwidth = float(metadata['samplerate']) / float(self.bitrate) + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.bitrate = bitrates[self.options['signalling']] + self.bitwidth = float(self.samplerate) / float(self.bitrate) + self.halfbit = int(self.bitwidth / 2) def putpx(self, data): - self.put(self.samplenum, self.samplenum, self.out_proto, data) + self.put(self.samplenum, self.samplenum, self.out_python, data) def putx(self, data): self.put(self.samplenum, self.samplenum, self.out_ann, data) + def putpm(self, data): + s, h = self.samplenum, self.halfbit + self.put(self.ss_block - h, s + h, self.out_python, data) + + def putm(self, data): + s, h = self.samplenum, self.halfbit + self.put(self.ss_block - h, s + h, self.out_ann, data) + def putpb(self, data): - s, halfbit = self.samplenum, int(self.bitwidth / 2) - self.put(s - halfbit, s + halfbit, self.out_proto, data) + s, h = self.samplenum, self.halfbit + self.put(s - h, s + h, self.out_python, data) def putb(self, data): - s, halfbit = self.samplenum, int(self.bitwidth / 2) - self.put(s - halfbit, s + halfbit, self.out_ann, data) + s, h = self.samplenum, self.halfbit + self.put(s - h, s + h, self.out_ann, data) def set_new_target_samplenum(self): bitpos = self.ss_sop + (self.bitwidth / 2) @@ -128,13 +162,16 @@ class Decoder(srd.Decoder): def handle_bit(self, sym, b): if self.consecutive_ones == 6 and b == '0': - # Stuff bit. Don't add to the packet, reset self.consecutive_ones. - self.putb([4, ['SB: %s/%s' % (sym, b)]]) + # Stuff bit. + self.putpb(['STUFF BIT', None]) + self.putb([4, ['SB: %s' % b]]) + self.putb([0, ['%s' % sym]]) self.consecutive_ones = 0 else: - # Normal bit. Add it to the packet, update self.consecutive_ones. - self.putb([3, ['%s/%s' % (sym, b)]]) - self.packet += b + # Normal bit (not a stuff bit). + self.putpb(['BIT', b]) + self.putb([3, ['%s' % b]]) + self.putb([0, ['%s' % sym]]) if b == '1': self.consecutive_ones += 1 else: @@ -149,16 +186,17 @@ class Decoder(srd.Decoder): self.set_new_target_samplenum() self.oldsym = sym if self.syms[-2:] == ['SE0', 'J']: - # Got an EOP, i.e. we now have a full packet. - self.putpb(['PACKET', self.packet]) - self.putb([5, ['PACKET: %s' % self.packet]]) - self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE' + # Got an EOP. + self.putpm(['EOP', None]) + self.putm([2, ['EOP']]) + self.bitnum, self.syms, self.state = 0, [], 'IDLE' self.consecutive_ones = 0 def get_bit(self, sym): if sym == 'SE0': # Start of an EOP. Change state, run get_eop() for this bit. self.state = 'GET EOP' + self.ss_block = self.samplenum self.get_eop(sym) return self.syms.append(sym) @@ -170,6 +208,8 @@ class Decoder(srd.Decoder): self.oldsym = sym def decode(self, ss, es, data): + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") for (self.samplenum, pins) in data: # State machine. if self.state == 'IDLE':