X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=6f3ceffca75e771f22653b095bff6eaf74b877e1;hp=0d21d2226405a0814f32ebde93f6a5b479e9554a;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=f2a5df42ea41e6c4370d4efa1a27ab942ba1ddff diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index 0d21d22..6f3ceff 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -19,12 +19,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# USB signalling (low-speed and full-speed) protocol decoder - import sigrokdecode as srd ''' -Protocol output format: +OUTPUT_PYTHON format: Packet: [, ] @@ -82,9 +80,10 @@ class Decoder(srd.Decoder): {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, ] optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'full-speed', 'values': ('full-speed', 'low-speed')}, + ) annotations = [ ['sym', 'Symbol'], ['sop', 'Start of packet (SOP)'], @@ -92,6 +91,10 @@ class Decoder(srd.Decoder): ['bit', 'Bit'], ['stuffbit', 'Stuff bit'], ] + annotation_rows = ( + ('bits', 'Bits', (1, 2, 3, 4)), + ('symbols', 'Symbols', (0,)), + ) def __init__(self): self.samplerate = None @@ -109,8 +112,8 @@ class Decoder(srd.Decoder): self.state = 'IDLE' def start(self): - self.out_proto = self.add(srd.OUTPUT_PYTHON, 'usb_signalling') - self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling') + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: @@ -119,18 +122,15 @@ class Decoder(srd.Decoder): self.bitwidth = float(self.samplerate) / float(self.bitrate) self.halfbit = int(self.bitwidth / 2) - def report(self): - pass - def putpx(self, data): - self.put(self.samplenum, self.samplenum, self.out_proto, data) + self.put(self.samplenum, self.samplenum, self.out_python, data) def putx(self, data): self.put(self.samplenum, self.samplenum, self.out_ann, data) def putpm(self, data): s, h = self.samplenum, self.halfbit - self.put(self.ss_block - h, s + h, self.out_proto, data) + self.put(self.ss_block - h, s + h, self.out_python, data) def putm(self, data): s, h = self.samplenum, self.halfbit @@ -138,7 +138,7 @@ class Decoder(srd.Decoder): def putpb(self, data): s, h = self.samplenum, self.halfbit - self.put(s - h, s + h, self.out_proto, data) + self.put(s - h, s + h, self.out_python, data) def putb(self, data): s, h = self.samplenum, self.halfbit @@ -164,12 +164,14 @@ class Decoder(srd.Decoder): if self.consecutive_ones == 6 and b == '0': # Stuff bit. self.putpb(['STUFF BIT', None]) - self.putb([4, ['SB: %s/%s' % (sym, b)]]) + self.putb([4, ['SB: %s' % b]]) + self.putb([0, ['%s' % sym]]) self.consecutive_ones = 0 else: # Normal bit (not a stuff bit). self.putpb(['BIT', b]) - self.putb([3, ['%s/%s' % (sym, b)]]) + self.putb([3, ['%s' % b]]) + self.putb([0, ['%s' % sym]]) if b == '1': self.consecutive_ones += 1 else: