X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=626dcd0a3d00c40809227802d7f4f61fb3f813c1;hp=ae0f651a5de5a2ed384585a58a36b9b8992b65a7;hb=5d6d8896ded87ce72b42e68c77120008b2d1b779;hpb=c240da484645ab78b19c8a8e2938df67039660f0

diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py
index ae0f651..626dcd0 100644
--- a/decoders/usb_signalling/pd.py
+++ b/decoders/usb_signalling/pd.py
@@ -104,10 +104,11 @@ class Decoder(srd.Decoder):
     id = 'usb_signalling'
     name = 'USB signalling'
     longname = 'Universal Serial Bus (LS/FS) signalling'
-    desc = 'USB (low-speed and full-speed) signalling protocol.'
+    desc = 'USB (low-speed/full-speed) signalling protocol.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['usb_signalling']
+    tags = ['PC']
     channels = (
         {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
         {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
@@ -135,10 +136,12 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.oldsym = 'J' # The "idle" state is J.
         self.ss_block = None
-        self.samplenum = 0
         self.bitrate = None
         self.bitwidth = None
         self.samplepos = None
@@ -190,7 +193,7 @@ class Decoder(srd.Decoder):
         self.put(s, e, self.out_ann, data)
 
     def set_new_target_samplenum(self):
-        self.samplepos += self.bitwidth;
+        self.samplepos += self.bitwidth
         self.samplenum_target = int(self.samplepos)
         self.samplenum_lastedge = self.samplenum_edge
         self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
@@ -302,7 +305,7 @@ class Decoder(srd.Decoder):
             raise SamplerateError('Cannot decode without samplerate.')
 
         # Seed internal state from the very first sample.
-        pins = self.wait({'skip': 1})
+        pins = self.wait()
         sym = symbols[self.options['signalling']][pins]
         self.handle_idle(sym)
 
@@ -330,7 +333,7 @@ class Decoder(srd.Decoder):
                     self.get_eop(sym)
             elif self.state == 'WAIT IDLE':
                 # Skip "all-low" input. Wait for high level on either DP or DM.
-                pins = self.wait({'skip': 1})
+                pins = self.wait()
                 while not pins[0] and not pins[1]:
                     pins = self.wait([{0: 'h'}, {1: 'h'}])
                 if self.samplenum - self.samplenum_lastedge > 1: