X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fusb_signalling%2Fpd.py;h=0ad8fdc707d53c6dead64d65200268abbe37f0c1;hp=e6b729919a1a9161dfe4e92ed4d1a9cac3f25a4c;hb=4539e9ca58966ce3c9cad4801b16c315e86ace01;hpb=9e1437a045ef0c7df7e847be148fac6b4c0bbb4b diff --git a/decoders/usb_signalling/pd.py b/decoders/usb_signalling/pd.py index e6b7299..0ad8fdc 100644 --- a/decoders/usb_signalling/pd.py +++ b/decoders/usb_signalling/pd.py @@ -1,8 +1,8 @@ ## -## This file is part of the sigrok project. +## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2011 Gareth McMullin -## Copyright (C) 2012 Uwe Hermann +## Copyright (C) 2012-2013 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -15,33 +15,92 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## -# USB signalling (low-speed and full-speed) protocol decoder - import sigrokdecode as srd -# Low-/full-speed symbols (used as states of our state machine, too). +''' +OUTPUT_PYTHON format: + +Packet: +[, ] + +, : + - 'SOP', None + - 'SYM', + - 'BIT', + - 'STUFF BIT', None + - 'EOP', None + - 'ERR', None + - 'KEEP ALIVE', None + - 'RESET', None + +: + - 'J', 'K', 'SE0', or 'SE1' + +: + - '0' or '1' + - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'. +''' + +# Low-/full-speed symbols. # Note: Low-speed J and K are inverted compared to the full-speed J and K! -symbols_ls = { +symbols = { + 'low-speed': { # (, ): (0, 0): 'SE0', (1, 0): 'K', (0, 1): 'J', (1, 1): 'SE1', -} -symbols_fs = { + }, + 'full-speed': { + # (, ): + (0, 0): 'SE0', + (1, 0): 'J', + (0, 1): 'K', + (1, 1): 'SE1', + }, + 'automatic': { + # (, ): + (0, 0): 'SE0', + (1, 0): 'FS_J', + (0, 1): 'LS_J', + (1, 1): 'SE1', + }, + # After a PREamble PID, the bus segment between Host and Hub uses LS + # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For + # both upstream and downstream low-speed data, the hub is responsible for + # inverting the polarity of the data before transmitting to/from a + # low-speed port."). + 'low-speed-rp': { # (, ): (0, 0): 'SE0', (1, 0): 'J', (0, 1): 'K', (1, 1): 'SE1', + }, } +bitrates = { + 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%) + 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%) + 'full-speed': 12000000, # 12Mb/s (+/- 0.25%) + 'automatic': None +} + +sym_annotation = { + 'J': [0, ['J']], + 'K': [1, ['K']], + 'SE0': [2, ['SE0', '0']], + 'SE1': [3, ['SE1', '1']], +} + +class SamplerateError(Exception): + pass + class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'usb_signalling' name = 'USB signalling' longname = 'Universal Serial Bus (LS/FS) signalling' @@ -49,104 +108,237 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['usb_signalling'] - probes = [ + channels = ( {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'}, {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'}, - ] - optional_probes = [] - options = { - 'signalling': ['Signalling', 'full-speed'], - } - annotations = [ - ['Text', 'Human-readable text'] - ] + ) + options = ( + {'id': 'signalling', 'desc': 'Signalling', + 'default': 'automatic', 'values': ('automatic', 'full-speed', 'low-speed')}, + ) + annotations = ( + ('sym-j', 'J symbol'), + ('sym-k', 'K symbol'), + ('sym-se0', 'SE0 symbol'), + ('sym-se1', 'SE1 symbol'), + ('sop', 'Start of packet (SOP)'), + ('eop', 'End of packet (EOP)'), + ('bit', 'Bit'), + ('stuffbit', 'Stuff bit'), + ('error', 'Error'), + ('keep-alive', 'Low-speed keep-alive'), + ('reset', 'Reset'), + ) + annotation_rows = ( + ('bits', 'Bits', (4, 5, 6, 7, 8, 9, 10)), + ('symbols', 'Symbols', (0, 1, 2, 3)), + ) def __init__(self): - self.sym = 'J' # The "idle" state is J. + self.samplerate = None + self.oldsym = 'J' # The "idle" state is J. + self.ss_block = None self.samplenum = 0 - self.scount = 0 - self.packet = '' - self.syms = [] + self.bitrate = None + self.bitwidth = None + self.samplepos = None + self.samplenum_target = None + self.samplenum_edge = None + self.samplenum_lastedge = 0 self.oldpins = None + self.edgepins = None + self.consecutive_ones = 0 + self.bits = None + self.state = 'INIT' - def start(self, metadata): - self.samplerate = metadata['samplerate'] - self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling') - self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling') + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + self.signalling = self.options['signalling'] + if self.signalling != 'automatic': + self.update_bitrate() - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: + def update_bitrate(self): + self.bitrate = bitrates[self.signalling] + self.bitwidth = float(self.samplerate) / float(self.bitrate) + + def putpx(self, data): + s = self.samplenum_edge + self.put(s, s, self.out_python, data) + + def putx(self, data): + s = self.samplenum_edge + self.put(s, s, self.out_ann, data) + + def putpm(self, data): + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_python, data) + + def putm(self, data): + e = self.samplenum_edge + self.put(self.ss_block, e, self.out_ann, data) + + def putpb(self, data): + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_python, data) + + def putb(self, data): + s, e = self.samplenum_lastedge, self.samplenum_edge + self.put(s, e, self.out_ann, data) + + def set_new_target_samplenum(self): + self.samplepos += self.bitwidth; + self.samplenum_target = int(self.samplepos) + self.samplenum_lastedge = self.samplenum_edge + self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2)) + + def wait_for_sop(self, sym): + # Wait for a Start of Packet (SOP), i.e. a J->K symbol change. + if sym != 'K' or self.oldsym != 'J': + return + self.consecutive_ones = 0 + self.bits = '' + self.update_bitrate() + self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5 + self.set_new_target_samplenum() + self.putpx(['SOP', None]) + self.putx([4, ['SOP', 'S']]) + self.state = 'GET BIT' - # Note: self.samplenum is the absolute sample number, whereas - # self.scount only counts the number of samples since the - # last change in the D+/D- lines. - self.scount += 1 - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (dp, dm) = pins, pins - - if self.options['signalling'] == 'low-speed': - sym = symbols_ls[dp, dm] - elif self.options['signalling'] == 'full-speed': - sym = symbols_fs[dp, dm] - - self.put(0, 0, self.out_ann, [0, [sym]]) - self.put(0, 0, self.out_proto, ['SYM', sym]) - - # Wait for a symbol change (i.e., change in D+/D- lines). - if sym == self.sym: - continue - - ## # Debug code: - ## self.syms.append(sym + ' ') - ## if len(self.syms) == 16: - ## self.put(0, 0, self.out_ann, [0, [''.join(self.syms)]]) - ## self.syms = [] - # continue - - # How many bits since the last transition? - if self.packet != '' or self.sym != 'J': - if self.options['signalling'] == 'low-speed': - bitrate = 1500000 # 1.5Mb/s (+/- 1.5%) - elif self.options['signalling'] == 'full-speed': - bitrate = 12000000 # 12Mb/s (+/- 0.25%) - bitcount = int((self.scount - 1) * bitrate / self.samplerate) + def handle_bit(self, b): + if self.consecutive_ones == 6: + if b == '0': + # Stuff bit. + self.putpb(['STUFF BIT', None]) + self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']]) + self.consecutive_ones = 0 else: - bitcount = 0 - - if self.sym == 'SE0': - if bitcount == 1: - # End-Of-Packet (EOP) - # self.put(0, 0, self.out_ann, - # [0, [packet_decode(self.packet), self.packet]]) - if self.packet != '': # FIXME? - self.put(0, 0, self.out_ann, [0, ['PACKET: %s' % self.packet]]) - self.put(0, 0, self.out_proto, ['PACKET', self.packet]) + self.putpb(['ERR', None]) + self.putb([8, ['Bit stuff error', 'BS ERR', 'B']]) + self.state = 'IDLE' + else: + # Normal bit (not a stuff bit). + self.putpb(['BIT', b]) + self.putb([6, ['%s' % b]]) + if b == '1': + self.consecutive_ones += 1 + else: + self.consecutive_ones = 0 + + def get_eop(self, sym): + # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J. + self.set_new_target_samplenum() + self.putpb(['SYM', sym]) + self.putb(sym_annotation[sym]) + self.oldsym = sym + if sym == 'SE0': + pass + elif sym == 'J': + # Got an EOP. + self.putpm(['EOP', None]) + self.putm([5, ['EOP', 'E']]) + self.state = 'WAIT IDLE' + else: + self.putpm(['ERR', None]) + self.putm([8, ['EOP Error', 'EErr', 'E']]) + self.state = 'IDLE' + + def get_bit(self, sym): + self.set_new_target_samplenum() + b = '0' if self.oldsym != sym else '1' + self.oldsym = sym + if sym == 'SE0': + # Start of an EOP. Change state, save edge + self.state = 'GET EOP' + self.ss_block = self.samplenum_lastedge + else: + self.handle_bit(b) + self.putpb(['SYM', sym]) + self.putb(sym_annotation[sym]) + if len(self.bits) <= 16: + self.bits += b + if len(self.bits) == 16 and self.bits == '0000000100111100': + # Sync and low-speed PREamble seen + self.putpx(['EOP', None]) + self.state = 'IDLE' + self.signalling = 'low-speed-rp' + self.update_bitrate() + self.oldsym = 'J' + if b == '0': + edgesym = symbols[self.signalling][tuple(self.edgepins)] + if edgesym not in ('SE0', 'SE1'): + if edgesym == sym: + self.bitwidth = self.bitwidth - (0.001 * self.bitwidth) + self.samplepos = self.samplepos - (0.01 * self.bitwidth) else: - # Longer than EOP, assume reset. - self.put(0, 0, self.out_ann, [0, ['RESET']]) - self.put(0, 0, self.out_proto, ['RESET', None]) - # self.put(0, 0, self.out_ann, [0, [self.packet]]) - self.scount = 0 - self.sym = sym - self.packet = '' - continue - - # Add bits to the packet string. - self.packet += '1' * bitcount - - # Handle bit stuffing. - if bitcount < 6 and sym != 'SE0': - self.packet += '0' - elif bitcount > 6: - self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']]) - self.put(0, 0, self.out_proto, ['BIT STUFF ERROR', None]) - - self.scount = 0 - self.sym = sym + self.bitwidth = self.bitwidth + (0.001 * self.bitwidth) + self.samplepos = self.samplepos + (0.01 * self.bitwidth) + + def handle_idle(self, sym): + self.samplenum_edge = self.samplenum + se0_length = float(self.samplenum - self.samplenum_lastedge) / self.samplerate + if se0_length > 2.5e-6: # 2.5us + self.putpb(['RESET', None]) + self.putb([10, ['Reset', 'Res', 'R']]) + self.signalling = self.options['signalling'] + elif se0_length > 1.2e-6 and self.signalling == 'low-speed': + self.putpb(['KEEP ALIVE', None]) + self.putb([9, ['Keep-alive', 'KA', 'A']]) + + if sym == 'FS_J': + self.signalling = 'full-speed' + self.update_bitrate() + elif sym == 'LS_J': + self.signalling = 'low-speed' + self.update_bitrate() + self.oldsym = 'J' + self.state = 'IDLE' + def decode(self, ss, es, data): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') + for (self.samplenum, pins) in data: + # State machine. + if self.state == 'IDLE': + # Ignore identical samples early on (for performance reasons). + if self.oldpins == pins: + continue + self.oldpins = pins + sym = symbols[self.signalling][tuple(pins)] + if sym == 'SE0': + self.samplenum_lastedge = self.samplenum + self.state = 'WAIT IDLE' + else: + self.wait_for_sop(sym) + self.edgepins = pins + elif self.state in ('GET BIT', 'GET EOP'): + # Wait until we're in the middle of the desired bit. + if self.samplenum == self.samplenum_edge: + self.edgepins = pins + if self.samplenum < self.samplenum_target: + continue + sym = symbols[self.signalling][tuple(pins)] + if self.state == 'GET BIT': + self.get_bit(sym) + elif self.state == 'GET EOP': + self.get_eop(sym) + self.oldpins = pins + elif self.state == 'WAIT IDLE': + if tuple(pins) == (0, 0): + continue + if self.samplenum - self.samplenum_lastedge > 1: + sym = symbols[self.options['signalling']][tuple(pins)] + self.handle_idle(sym) + else: + sym = symbols[self.signalling][tuple(pins)] + self.wait_for_sop(sym) + self.oldpins = pins + self.edgepins = pins + elif self.state == 'INIT': + sym = symbols[self.options['signalling']][tuple(pins)] + self.handle_idle(sym) + self.oldpins = pins