X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=6c9fdee8087e967e041e4e7b8de4e9335b05baa9;hp=16048346d1bd70d06053fd5dc4b07a4dd766f003;hb=122e9a90a54e034b93f554938896983d293edec1;hpb=a7fc4c342689ab3b42cd8e662612e12aee8a2bf3

diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py
index 1604834..6c9fdee 100644
--- a/decoders/uart/uart.py
+++ b/decoders/uart/uart.py
@@ -18,19 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-#
 # UART protocol decoder
-#
 
 import sigrokdecode as srd
 
-# States
-WAIT_FOR_START_BIT = 0
-GET_START_BIT = 1
-GET_DATA_BITS = 2
-GET_PARITY_BIT = 3
-GET_STOP_BITS = 4
-
 # Used for differentiating between the two data directions.
 RX = 0
 TX = 1
@@ -71,7 +62,6 @@ class Decoder(srd.Decoder):
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
     desc = 'Universal Asynchronous Receiver/Transmitter (UART)'
-    longdesc = 'TODO.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
@@ -111,10 +101,7 @@ class Decoder(srd.Decoder):
         self.paritybit = [-1, -1]
         self.stopbit1 = [-1, -1]
         self.startsample = [-1, -1]
-
-        # Initial state.
-        self.state = [WAIT_FOR_START_BIT, WAIT_FOR_START_BIT]
-
+        self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
         self.oldbit = [None, None]
 
     def start(self, metadata):
@@ -155,7 +142,7 @@ class Decoder(srd.Decoder):
         # Save the sample number where the start bit begins.
         self.frame_start[rxtx] = self.samplenum
 
-        self.state[rxtx] = GET_START_BIT
+        self.state[rxtx] = 'GET START BIT'
 
     def get_start_bit(self, rxtx, signal):
         # Skip samples until we're in the middle of the start bit.
@@ -174,7 +161,7 @@ class Decoder(srd.Decoder):
         self.databyte[rxtx] = 0
         self.startsample[rxtx] = -1
 
-        self.state[rxtx] = GET_DATA_BITS
+        self.state[rxtx] = 'GET DATA BITS'
 
         self.put(self.frame_start[rxtx], self.samplenum, self.out_proto,
                  ['STARTBIT', rxtx, self.startbit[rxtx]])
@@ -208,7 +195,7 @@ class Decoder(srd.Decoder):
             self.cur_data_bit[rxtx] += 1
             return
 
-        self.state[rxtx] = GET_PARITY_BIT
+        self.state[rxtx] = 'GET PARITY BIT'
 
         self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto,
                  ['DATA', rxtx, self.databyte[rxtx]])
@@ -226,7 +213,7 @@ class Decoder(srd.Decoder):
     def get_parity_bit(self, rxtx, signal):
         # If no parity is used/configured, skip to the next state immediately.
         if self.options['parity_type'] == 'none':
-            self.state[rxtx] = GET_STOP_BITS
+            self.state[rxtx] = 'GET STOP BITS'
             return
 
         # Skip samples until we're in the middle of the parity bit.
@@ -235,7 +222,7 @@ class Decoder(srd.Decoder):
 
         self.paritybit[rxtx] = signal
 
-        self.state[rxtx] = GET_STOP_BITS
+        self.state[rxtx] = 'GET STOP BITS'
 
         if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
                      self.databyte[rxtx], self.options['num_data_bits']):
@@ -268,7 +255,7 @@ class Decoder(srd.Decoder):
                      ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
             # TODO: Abort? Ignore the frame? Other?
 
-        self.state[rxtx] = WAIT_FOR_START_BIT
+        self.state[rxtx] = 'WAIT FOR START BIT'
 
         # TODO: Fix range.
         self.put(self.samplenum, self.samplenum, self.out_proto,
@@ -295,15 +282,15 @@ class Decoder(srd.Decoder):
             for rxtx in (RX, TX):
                 signal = rx if (rxtx == RX) else tx
 
-                if self.state[rxtx] == WAIT_FOR_START_BIT:
+                if self.state[rxtx] == 'WAIT FOR START BIT':
                     self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
-                elif self.state[rxtx] == GET_START_BIT:
+                elif self.state[rxtx] == 'GET START BIT':
                     self.get_start_bit(rxtx, signal)
-                elif self.state[rxtx] == GET_DATA_BITS:
+                elif self.state[rxtx] == 'GET DATA BITS':
                     self.get_data_bits(rxtx, signal)
-                elif self.state[rxtx] == GET_PARITY_BIT:
+                elif self.state[rxtx] == 'GET PARITY BIT':
                     self.get_parity_bit(rxtx, signal)
-                elif self.state[rxtx] == GET_STOP_BITS:
+                elif self.state[rxtx] == 'GET STOP BITS':
                     self.get_stop_bits(rxtx, signal)
                 else:
                     raise Exception('Invalid state: %d' % self.state[rxtx])