X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fuart.py;h=4ceaef6423cb14a75a765382173a50dbe11df48c;hp=a0f915cc2da2183f291fdbd11f7928a02b5906f0;hb=8e828d2a29154fb9cae8c9c38d27c60f820dd584;hpb=decde15ecb51b3326b31019af61e0a729b9c61d0 diff --git a/decoders/uart/uart.py b/decoders/uart/uart.py index a0f915c..4ceaef6 100644 --- a/decoders/uart/uart.py +++ b/decoders/uart/uart.py @@ -22,98 +22,6 @@ # UART protocol decoder # -# -# Universal Asynchronous Receiver Transmitter (UART) is a simple serial -# communication protocol which allows two devices to talk to each other. -# -# It uses just two data signals and a ground (GND) signal: -# - RX/RXD: Receive signal -# - TX/TXD: Transmit signal -# -# The protocol is asynchronous, i.e., there is no dedicated clock signal. -# Rather, both devices have to agree on a baudrate (number of bits to be -# transmitted per second) beforehand. Baudrates can be arbitrary in theory, -# but usually the choice is limited by the hardware UARTs that are used. -# Common values are 9600 or 115200. -# -# The protocol allows full-duplex transmission, i.e. both devices can send -# data at the same time. However, unlike SPI (which is always full-duplex, -# i.e., each send operation is automatically also a receive operation), UART -# allows one-way communication, too. In such a case only one signal (and GND) -# is required. -# -# The data is sent over the TX line in so-called 'frames', which consist of: -# - Exactly one start bit (always 0/low). -# - Between 5 and 9 data bits. -# - An (optional) parity bit. -# - One or more stop bit(s). -# -# The idle state of the RX/TX line is 1/high. As the start bit is 0/low, the -# receiver can continually monitor its RX line for a falling edge, in order -# to detect the start bit. -# -# Once detected, it can (due to the agreed-upon baudrate and thus the known -# width/duration of one UART bit) sample the state of the RX line "in the -# middle" of each (start/data/parity/stop) bit it wants to analyze. -# -# It is configurable whether there is a parity bit in a frame, and if yes, -# which type of parity is used: -# - None: No parity bit is included. -# - Odd: The number of 1 bits in the data (and parity bit itself) is odd. -# - Even: The number of 1 bits in the data (and parity bit itself) is even. -# - Mark/one: The parity bit is always 1/high (also called 'mark state'). -# - Space/zero: The parity bit is always 0/low (also called 'space state'). -# -# It is also configurable how many stop bits are to be used: -# - 1 stop bit (most common case) -# - 2 stop bits -# - 1.5 stop bits (i.e., one stop bit, but 1.5 times the UART bit width) -# - 0.5 stop bits (i.e., one stop bit, but 0.5 times the UART bit width) -# -# The bit order of the 5-9 data bits is LSB-first. -# -# Possible special cases: -# - One or both data lines could be inverted, which also means that the idle -# state of the signal line(s) is low instead of high. -# - Only the data bits on one or both data lines (and the parity bit) could -# be inverted (but the start/stop bits remain non-inverted). -# - The bit order could be MSB-first instead of LSB-first. -# - The baudrate could change in the middle of the communication. This only -# happens in very special cases, and can only work if both devices know -# to which baudrate they are to switch, and when. -# - Theoretically, the baudrate on RX and the one on TX could also be -# different, but that's a very obscure case and probably doesn't happen -# very often in practice. -# -# Error conditions: -# - If there is a parity bit, but it doesn't match the expected parity, -# this is called a 'parity error'. -# - If there are no stop bit(s), that's called a 'frame error'. -# -# More information: -# TODO: URLs -# - -# -# Protocol output format: -# -# UART packet: -# [, , ] -# -# This is the list of s and their respective : -# - T_START: The data is the (integer) value of the start bit (0 or 1). -# - T_DATA: The data is the (integer) value of the UART data. Valid values -# range from 0 to 512 (as the data can be up to 9 bits in size). -# - T_PARITY: The data is the (integer) value of the parity bit (0 or 1). -# - T_STOP: The data is the (integer) value of the stop bit (0 or 1). -# - T_INVALID_START: The data is the (integer) value of the start bit (0 or 1). -# - T_INVALID_STOP: The data is the (integer) value of the stop bit (0 or 1). -# - T_PARITY_ERROR: The data is a tuple with two entries. The first one is -# the expected parity value, the second is the actual parity value. -# -# The field is 0 for RX packets, 1 for TX packets. -# - import sigrokdecode as srd # States @@ -151,15 +59,6 @@ ANN_HEX = 2 ANN_OCT = 3 ANN_BITS = 4 -# Protocol output packet types -T_START = 0 -T_DATA = 1 -T_PARITY = 2 -T_STOP = 3 -T_INVALID_START = 4 -T_INVALID_STOP = 5 -T_PARITY_ERROR = 6 - # Given a parity type to check (odd, even, zero, one), the value of the # parity bit, the value of the data, and the length of the data (5-9 bits, # usually 8 bits) return True if the parity is correct, False otherwise. @@ -173,13 +72,13 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits): return parity_bit == 1 # Count number of 1 (high) bits in the data (and the parity bit itself!). - parity = bin(data).count('1') + parity_bit + ones = bin(data).count('1') + parity_bit # Check for odd/even parity. if parity_type == PARITY_ODD: - return (parity % 2) == 1 + return (ones % 2) == 1 elif parity_type == PARITY_EVEN: - return (parity % 2) == 0 + return (ones % 2) == 0 else: raise Exception('Invalid parity type: %d' % parity_type) @@ -199,12 +98,12 @@ class Decoder(srd.Decoder): {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, ] - extra_probes = [] + optional_probes = [] options = { 'baudrate': ['Baud rate', 115200], 'num_data_bits': ['Data bits', 8], # Valid: 5-9. - 'parity': ['Parity', PARITY_NONE], # TODO: Rename to parity_type. - 'parity_check': ['Check parity', True], # TODO: Bool supported? + 'parity_type': ['Parity type', PARITY_NONE], + 'parity_check': ['Check parity?', True], # TODO: Bool supported? 'num_stop_bits': ['Stop bit(s)', STOP_BITS_1], 'bit_order': ['Bit order', LSB_FIRST], # TODO: Options to invert the signal(s). @@ -226,6 +125,7 @@ class Decoder(srd.Decoder): self.startbit = [-1, -1] self.cur_data_bit = [0, 0] self.databyte = [0, 0] + self.paritybit = [-1, -1] self.stopbit1 = [-1, -1] self.startsample = [-1, -1] @@ -284,7 +184,7 @@ class Decoder(srd.Decoder): # The startbit must be 0. If not, we report an error. if self.startbit[rxtx] != 0: self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - [T_INVALID_START, rxtx, self.startbit[rxtx]]) + ['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) # TODO: Abort? Ignore rest of the frame? self.cur_data_bit[rxtx] = 0 @@ -294,7 +194,7 @@ class Decoder(srd.Decoder): self.state[rxtx] = GET_DATA_BITS self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - [T_START, rxtx, self.startbit[rxtx]]) + ['STARTBIT', rxtx, self.startbit[rxtx]]) self.put(self.frame_start[rxtx], self.samplenum, self.out_ann, [ANN_ASCII, ['Start bit', 'Start', 'S']]) @@ -310,7 +210,8 @@ class Decoder(srd.Decoder): # Get the next data bit in LSB-first or MSB-first fashion. if self.options['bit_order'] == LSB_FIRST: self.databyte[rxtx] >>= 1 - self.databyte[rxtx] |= (signal << (self.options['num_data_bits'] - 1)) + self.databyte[rxtx] |= \ + (signal << (self.options['num_data_bits'] - 1)) elif self.options['bit_order'] == MSB_FIRST: self.databyte[rxtx] <<= 1 self.databyte[rxtx] |= (signal << 0) @@ -327,7 +228,7 @@ class Decoder(srd.Decoder): self.state[rxtx] = GET_PARITY_BIT self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto, - [T_DATA, rxtx, self.databyte[rxtx]]) + ['DATA', rxtx, self.databyte[rxtx]]) s = 'RX: ' if (rxtx == RX) else 'TX: ' self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]]) @@ -341,7 +242,7 @@ class Decoder(srd.Decoder): def get_parity_bit(self, rxtx, signal): # If no parity is used/configured, skip to the next state immediately. - if self.options['parity'] == PARITY_NONE: + if self.options['parity_type'] == PARITY_NONE: self.state[rxtx] = GET_STOP_BITS return @@ -353,25 +254,25 @@ class Decoder(srd.Decoder): self.state[rxtx] = GET_STOP_BITS - if parity_ok(self.options['parity'], self.paritybit[rxtx], + if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.databyte[rxtx], self.options['num_data_bits']): # TODO: Fix range. self.put(self.samplenum, self.samplenum, self.out_proto, - [T_PARITY_BIT, rxtx, self.paritybit[rxtx]]) + ['PARITYBIT', rxtx, self.paritybit[rxtx]]) self.put(self.samplenum, self.samplenum, self.out_ann, [ANN_ASCII, ['Parity bit', 'Parity', 'P']]) else: # TODO: Fix range. # TODO: Return expected/actual parity values. self.put(self.samplenum, self.samplenum, self.out_proto, - [T_PARITY_ERROR, rxtx, (0, 1)]) # FIXME: Dummy tuple... + ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... self.put(self.samplenum, self.samplenum, self.out_ann, [ANN_ASCII, ['Parity error', 'Parity err', 'PE']]) # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity'] == PARITY_NONE else 1 + skip_parity = 0 if self.options['parity_type'] == PARITY_NONE else 1 b = self.options['num_data_bits'] + 1 + skip_parity if not self.reached_bit(rxtx, b): return @@ -381,14 +282,14 @@ class Decoder(srd.Decoder): # Stop bits must be 1. If not, we report an error. if self.stopbit1[rxtx] != 1: self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - [T_INVALID_STOP, rxtx, self.stopbit1[rxtx]]) + ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) # TODO: Abort? Ignore the frame? Other? self.state[rxtx] = WAIT_FOR_START_BIT # TODO: Fix range. self.put(self.samplenum, self.samplenum, self.out_proto, - [T_STOP, rxtx, self.stopbit1[rxtx]]) + ['STOPBIT', rxtx, self.stopbit1[rxtx]]) self.put(self.samplenum, self.samplenum, self.out_ann, [ANN_ASCII, ['Stop bit', 'Stop', 'P']])