X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=ffacad9acfb6c83c65058b59a4cbda159d6a2b01;hp=0fa0e7ff442b8e307a883cbd9711b646be9372cd;hb=03a986ea61ec565b5e366b950759d4ad753d3aea;hpb=ea36c1988829b9f8e9385ff6e5e506e3cab46877 diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 0fa0e7f..ffacad9 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -14,11 +14,11 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd +from common.srdhelper import bitpack from math import floor, ceil ''' @@ -76,7 +76,7 @@ class ChannelError(Exception): pass class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'uart' name = 'UART' longname = 'Universal Asynchronous Receiver/Transmitter' @@ -124,14 +124,18 @@ class Decoder(srd.Decoder): ('tx-warnings', 'TX warnings'), ('rx-data-bits', 'RX data bits'), ('tx-data-bits', 'TX data bits'), + ('rx-break', 'RX break'), + ('tx-break', 'TX break'), ) annotation_rows = ( ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), ('rx-warnings', 'RX warnings', (10,)), + ('rx-break', 'RX break', (14,)), ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-data-bits', 'TX bits', (13,)), ('tx-warnings', 'TX warnings', (11,)), + ('tx-break', 'TX break', (15,)), ) binary = ( ('rx', 'RX dump'), @@ -156,11 +160,20 @@ class Decoder(srd.Decoder): s, halfbit = self.samplenum, self.bit_width / 2.0 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) + def putgse(self, ss, es, data): + self.put(ss, es, self.out_ann, data) + + def putpse(self, ss, es, data): + self.put(ss, es, self.out_python, data) + def putbin(self, rxtx, data): s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) def __init__(self): + self.reset() + + def reset(self): self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] @@ -171,9 +184,8 @@ class Decoder(srd.Decoder): self.stopbit1 = [-1, -1] self.startsample = [-1, -1] self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] - self.oldbit = [1, 1] - self.oldpins = [-1, -1] self.databits = [[], []] + self.break_start = [None, None] def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) @@ -187,8 +199,8 @@ class Decoder(srd.Decoder): # The width of one UART bit in number of samples. self.bit_width = float(self.samplerate) / float(self.options['baudrate']) - # Return true if we reached the middle of the desired bit, false otherwise. - def reached_bit(self, rxtx, bitnum): + def get_sample_point(self, rxtx, bitnum): + # Determine absolute sample number of a bit slot's sample point. # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). @@ -196,32 +208,15 @@ class Decoder(srd.Decoder): # index of the middle sample within bit window is (bit_width - 1) / 2. bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0 bitpos += bitnum * self.bit_width - if self.samplenum >= bitpos: - return True - return False - - def reached_bit_last(self, rxtx, bitnum): - bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) - if self.samplenum >= bitpos: - return True - return False - - def wait_for_start_bit(self, rxtx, old_signal, signal): - # The start bit is always 0 (low). As the idle UART (and the stop bit) - # level is 1 (high), the beginning of a start bit is a falling edge. - if not (old_signal == 1 and signal == 0): - return + return bitpos + def wait_for_start_bit(self, rxtx, signal): # Save the sample number where the start bit begins. self.frame_start[rxtx] = self.samplenum self.state[rxtx] = 'GET START BIT' def get_start_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the start bit. - if not self.reached_bit(rxtx, 0): - return - self.startbit[rxtx] = signal # The startbit must be 0. If not, we report an error and wait @@ -236,29 +231,16 @@ class Decoder(srd.Decoder): self.datavalue[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = 'GET DATA BITS' - self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) - def get_data_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the desired data bit. - if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): - return + self.state[rxtx] = 'GET DATA BITS' + def get_data_bits(self, rxtx, signal): # Save the sample number of the middle of the first data bit. if self.startsample[rxtx] == -1: self.startsample[rxtx] = self.samplenum - # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == 'lsb-first': - self.datavalue[rxtx] >>= 1 - self.datavalue[rxtx] |= \ - (signal << (self.options['num_data_bits'] - 1)) - else: - self.datavalue[rxtx] <<= 1 - self.datavalue[rxtx] |= (signal << 0) - self.putg([rxtx + 12, ['%d' % signal]]) # Store individual data bits and their start/end samplenumbers. @@ -266,12 +248,15 @@ class Decoder(srd.Decoder): self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) # Return here, unless we already received all data bits. - if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: - self.cur_data_bit[rxtx] += 1 + self.cur_data_bit[rxtx] += 1 + if self.cur_data_bit[rxtx] < self.options['num_data_bits']: return - self.state[rxtx] = 'GET PARITY BIT' - + # Convert accumulated data bits to a data value. + bits = [b[0] for b in self.databits[rxtx]] + if self.options['bit_order'] == 'msb-first': + bits.reverse() + self.datavalue[rxtx] = bitpack(bits) self.putpx(rxtx, ['DATA', rxtx, (self.datavalue[rxtx], self.databits[rxtx])]) @@ -286,6 +271,12 @@ class Decoder(srd.Decoder): self.databits[rxtx] = [] + # Advance to either reception of the parity bit, or reception of + # the STOP bits if parity is not applicable. + self.state[rxtx] = 'GET PARITY BIT' + if self.options['parity_type'] == 'none': + self.state[rxtx] = 'GET STOP BITS' + def format_value(self, v): # Format value 'v' according to configured options. # Reflects the user selected kind of representation, as well as @@ -329,19 +320,8 @@ class Decoder(srd.Decoder): return None def get_parity_bit(self, rxtx, signal): - # If no parity is used/configured, skip to the next state immediately. - if self.options['parity_type'] == 'none': - self.state[rxtx] = 'GET STOP BITS' - return - - # Skip samples until we're in the middle of the parity bit. - if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): - return - self.paritybit[rxtx] = signal - self.state[rxtx] = 'GET STOP BITS' - if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.datavalue[rxtx], self.options['num_data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) @@ -351,14 +331,10 @@ class Decoder(srd.Decoder): self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) + self.state[rxtx] = 'GET STOP BITS' + # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity_type'] == 'none' else 1 - b = self.options['num_data_bits'] + 1 + skip_parity - if not self.reached_bit(rxtx, b): - return - self.stopbit1[rxtx] = signal # Stop bits must be 1. If not, we report an error. @@ -367,52 +343,110 @@ class Decoder(srd.Decoder): self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) # TODO: Abort? Ignore the frame? Other? - self.state[rxtx] = 'WAIT FOR START BIT' - self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) - def decode(self, ss, es, data): + self.state[rxtx] = 'WAIT FOR START BIT' + + def handle_break(self, rxtx): + self.putpse(self.frame_start[rxtx], self.samplenum, + ['BREAK', rxtx, 0]) + self.putgse(self.frame_start[rxtx], self.samplenum, + [rxtx + 14, ['Break condition', 'Break', 'Brk', 'B']]) + self.state[rxtx] = 'WAIT FOR START BIT' + + def get_wait_cond(self, rxtx, inv): + # Return condititions that are suitable for Decoder.wait(). Those + # conditions either match the falling edge of the START bit, or + # the sample point of the next bit time. + state = self.state[rxtx] + if state == 'WAIT FOR START BIT': + return {rxtx: 'r' if inv else 'f'} + if state == 'GET START BIT': + bitnum = 0 + elif state == 'GET DATA BITS': + bitnum = 1 + self.cur_data_bit[rxtx] + elif state == 'GET PARITY BIT': + bitnum = 1 + self.options['num_data_bits'] + elif state == 'GET STOP BITS': + bitnum = 1 + self.options['num_data_bits'] + bitnum += 0 if self.options['parity_type'] == 'none' else 1 + want_num = ceil(self.get_sample_point(rxtx, bitnum)) + return {'skip': want_num - self.samplenum} + + def inspect_sample(self, rxtx, signal, inv): + # Inspect a sample returned by .wait() for the specified UART line. + if inv: + signal = not signal + + state = self.state[rxtx] + if state == 'WAIT FOR START BIT': + self.wait_for_start_bit(rxtx, signal) + elif state == 'GET START BIT': + self.get_start_bit(rxtx, signal) + elif state == 'GET DATA BITS': + self.get_data_bits(rxtx, signal) + elif state == 'GET PARITY BIT': + self.get_parity_bit(rxtx, signal) + elif state == 'GET STOP BITS': + self.get_stop_bits(rxtx, signal) + + def inspect_edge(self, rxtx, signal, inv): + # Inspect edges, independently from traffic, to detect break conditions. + if inv: + signal = not signal + if not signal: + # Signal went low. Start another interval. + self.break_start[rxtx] = self.samplenum + return + # Signal went high. Was there an extended period with low signal? + if self.break_start[rxtx] is None: + return + diff = self.samplenum - self.break_start[rxtx] + if diff >= self.break_min_sample_count: + self.handle_break(rxtx) + self.break_start[rxtx] = None + + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') - for (self.samplenum, pins) in data: - - # We want to skip identical samples for performance reasons but, - # for now, we can only do that when we are in the idle state - # (meaning both channels are waiting for the start bit). - if self.state == self.idle_state and self.oldpins == pins: - continue - - self.oldpins, (rx, tx) = pins, pins - - if self.options['invert_rx'] == 'yes': - rx = not rx - if self.options['invert_tx'] == 'yes': - tx = not tx - - # Either RX or TX (but not both) can be omitted. - has_pin = [rx in (0, 1), tx in (0, 1)] - if has_pin == [False, False]: - raise ChannelError('Either TX or RX (or both) pins required.') - - # State machine. - for rxtx in (RX, TX): - # Don't try to handle RX (or TX) if not supplied. - if not has_pin[rxtx]: - continue - - signal = rx if (rxtx == RX) else tx - - if self.state[rxtx] == 'WAIT FOR START BIT': - self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) - elif self.state[rxtx] == 'GET START BIT': - self.get_start_bit(rxtx, signal) - elif self.state[rxtx] == 'GET DATA BITS': - self.get_data_bits(rxtx, signal) - elif self.state[rxtx] == 'GET PARITY BIT': - self.get_parity_bit(rxtx, signal) - elif self.state[rxtx] == 'GET STOP BITS': - self.get_stop_bits(rxtx, signal) - - # Save current RX/TX values for the next round. - self.oldbit[rxtx] = signal + + has_pin = [self.has_channel(ch) for ch in (RX, TX)] + if has_pin == [False, False]: + raise ChannelError('Either TX or RX (or both) pins required.') + + opt = self.options + inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] + cond_data_idx = [None] * len(has_pin) + + # Determine the number of samples for a complete frame's time span. + # A period of low signal (at least) that long is a break condition. + frame_samples = 1 # START + frame_samples += self.options['num_data_bits'] + frame_samples += 0 if self.options['parity_type'] == 'none' else 1 + frame_samples += self.options['num_stop_bits'] + frame_samples *= self.bit_width + self.break_min_sample_count = ceil(frame_samples) + cond_edge_idx = [None] * len(has_pin) + + while True: + conds = [] + if has_pin[RX]: + cond_data_idx[RX] = len(conds) + conds.append(self.get_wait_cond(RX, inv[RX])) + cond_edge_idx[RX] = len(conds) + conds.append({RX: 'e'}) + if has_pin[TX]: + cond_data_idx[TX] = len(conds) + conds.append(self.get_wait_cond(TX, inv[TX])) + cond_edge_idx[TX] = len(conds) + conds.append({TX: 'e'}) + (rx, tx) = self.wait(conds) + if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]: + self.inspect_sample(RX, rx, inv[RX]) + if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]: + self.inspect_edge(RX, rx, inv[RX]) + if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]: + self.inspect_sample(TX, tx, inv[TX]) + if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]: + self.inspect_edge(TX, tx, inv[TX])