X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=fd8254c217d1602e2c6c46b3d3b43e24a5239127;hp=0a0d30729c6bcf85de4b2edd0040e251b5dc05cf;hb=3d2d91e0b30e2e421bf693f7f9f8aad0634084b3;hpb=ab0522b8722c883275c2d695471b0746ab7372a0 diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 0a0d307..fd8254c 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -43,6 +43,7 @@ This is the list of s and their respective values: - 'FRAME': The data is always a tuple containing two items: The (integer) value of the UART data, and a boolean which reflects the validity of the UART frame. + - 'IDLE': The data is always 0. The field is 0 for RX packets, 1 for TX packets. ''' @@ -55,7 +56,10 @@ TX = 1 # parity bit, the value of the data, and the length of the data (5-9 bits, # usually 8 bits) return True if the parity is correct, False otherwise. # 'none' is _not_ allowed as value for 'parity_type'. -def parity_ok(parity_type, parity_bit, data, num_data_bits): +def parity_ok(parity_type, parity_bit, data, data_bits): + + if parity_type == 'ignore': + return True # Handle easy cases first (parity bit is always 1 or 0). if parity_type == 'zero': @@ -96,26 +100,27 @@ class Decoder(srd.Decoder): ) options = ( {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, - {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, + {'id': 'data_bits', 'desc': 'Data bits', 'default': 8, 'values': (5, 6, 7, 8, 9)}, - {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', - 'values': ('none', 'odd', 'even', 'zero', 'one')}, - {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', - 'values': ('yes', 'no')}, - {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, + {'id': 'parity', 'desc': 'Parity', 'default': 'none', + 'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')}, + {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0, 'values': (0.0, 0.5, 1.0, 1.5)}, {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', 'values': ('lsb-first', 'msb-first')}, {'id': 'format', 'desc': 'Data format', 'default': 'hex', 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, - {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no', + {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no', 'values': ('yes', 'no')}, - {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', + {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no', 'values': ('yes', 'no')}, - {'id': 'rx_packet_delimiter', 'desc': 'RX packet delimiter (decimal)', + {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50}, + {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)', 'default': -1}, - {'id': 'tx_packet_delimiter', 'desc': 'TX packet delimiter (decimal)', + {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)', 'default': -1}, + {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1}, + {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1}, ) annotations = ( ('rx-data', 'RX data'), @@ -138,13 +143,13 @@ class Decoder(srd.Decoder): ('tx-packet', 'TX packet'), ) annotation_rows = ( - ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-data-bits', 'RX bits', (12,)), + ('rx-data', 'RX', (0, 2, 4, 6, 8)), ('rx-warnings', 'RX warnings', (10,)), ('rx-break', 'RX break', (14,)), ('rx-packets', 'RX packets', (16,)), - ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-data-bits', 'TX bits', (13,)), + ('tx-data', 'TX', (1, 3, 5, 7, 9)), ('tx-warnings', 'TX warnings', (11,)), ('tx-break', 'TX break', (15,)), ('tx-packets', 'TX packets', (17,)), @@ -191,7 +196,6 @@ class Decoder(srd.Decoder): def reset(self): self.samplerate = None - self.samplenum = 0 self.frame_start = [-1, -1] self.frame_valid = [None, None] self.startbit = [-1, -1] @@ -205,12 +209,13 @@ class Decoder(srd.Decoder): self.break_start = [None, None] self.packet_cache = [[], []] self.ss_packet, self.es_packet = [None, None], [None, None] + self.idle_start = [None, None] def start(self): self.out_python = self.register(srd.OUTPUT_PYTHON) self.out_binary = self.register(srd.OUTPUT_BINARY) self.out_ann = self.register(srd.OUTPUT_ANN) - self.bw = (self.options['num_data_bits'] + 7) // 8 + self.bw = (self.options['data_bits'] + 7) // 8 def metadata(self, key, value): if key == srd.SRD_CONF_SAMPLERATE: @@ -220,12 +225,16 @@ class Decoder(srd.Decoder): def get_sample_point(self, rxtx, bitnum): # Determine absolute sample number of a bit slot's sample point. - # bitpos is the samplenumber which is in the middle of the - # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit - # (if used) or the first stop bit, and so on). - # The samples within bit are 0, 1, ..., (bit_width - 1), therefore - # index of the middle sample within bit window is (bit_width - 1) / 2. - bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0 + # Counts for UART bits start from 0 (0 = start bit, 1..x = data, + # x+1 = parity bit (if used) or the first stop bit, and so on). + # Accept a position in the range of 1-99% of the full bit width. + # Assume 50% for invalid input specs for backwards compatibility. + perc = self.options['sample_point'] or 50 + if not perc or perc not in range(1, 100): + perc = 50 + perc /= 100.0 + bitpos = (self.bit_width - 1) * perc + bitpos += self.frame_start[rxtx] bitpos += bitnum * self.bit_width return bitpos @@ -261,16 +270,18 @@ class Decoder(srd.Decoder): self.state[rxtx] = 'GET DATA BITS' def handle_packet(self, rxtx): - opt = ('rx' if (rxtx == RX) else 'tx') + '_packet_delimiter' - delim = self.options[opt] - if delim == -1: + d = 'rx' if (rxtx == RX) else 'tx' + delim = self.options[d + '_packet_delim'] + plen = self.options[d + '_packet_len'] + if delim == -1 and plen == -1: return - # Cache data values until we see the delimiter. + # Cache data values until we see the delimiter and/or the specified + # packet length has been reached (whichever happens first). if len(self.packet_cache[rxtx]) == 0: self.ss_packet[rxtx] = self.startsample[rxtx] self.packet_cache[rxtx].append(self.datavalue[rxtx]) - if self.datavalue[rxtx] == delim: + if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen: self.es_packet[rxtx] = self.samplenum s = '' for b in self.packet_cache[rxtx]: @@ -295,7 +306,7 @@ class Decoder(srd.Decoder): # Return here, unless we already received all data bits. self.cur_data_bit[rxtx] += 1 - if self.cur_data_bit[rxtx] < self.options['num_data_bits']: + if self.cur_data_bit[rxtx] < self.options['data_bits']: return # Convert accumulated data bits to a data value. @@ -322,7 +333,7 @@ class Decoder(srd.Decoder): # Advance to either reception of the parity bit, or reception of # the STOP bits if parity is not applicable. self.state[rxtx] = 'GET PARITY BIT' - if self.options['parity_type'] == 'none': + if self.options['parity'] == 'none': self.state[rxtx] = 'GET STOP BITS' def format_value(self, v): @@ -330,7 +341,7 @@ class Decoder(srd.Decoder): # Reflects the user selected kind of representation, as well as # the number of data bits in the UART frames. - fmt, bits = self.options['format'], self.options['num_data_bits'] + fmt, bits = self.options['format'], self.options['data_bits'] # Assume "is printable" for values from 32 to including 126, # below 32 is "control" and thus not printable, above 127 is @@ -370,8 +381,8 @@ class Decoder(srd.Decoder): def get_parity_bit(self, rxtx, signal): self.paritybit[rxtx] = signal - if parity_ok(self.options['parity_type'], self.paritybit[rxtx], - self.datavalue[rxtx], self.options['num_data_bits']): + if parity_ok(self.options['parity'], self.paritybit[rxtx], + self.datavalue[rxtx], self.options['data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) else: @@ -401,6 +412,7 @@ class Decoder(srd.Decoder): (self.datavalue[rxtx], self.frame_valid[rxtx])]) self.state[rxtx] = 'WAIT FOR START BIT' + self.idle_start[rxtx] = self.frame_start[rxtx] + self.frame_len_sample_count def handle_break(self, rxtx): self.putpse(self.frame_start[rxtx], self.samplenum, @@ -421,13 +433,24 @@ class Decoder(srd.Decoder): elif state == 'GET DATA BITS': bitnum = 1 + self.cur_data_bit[rxtx] elif state == 'GET PARITY BIT': - bitnum = 1 + self.options['num_data_bits'] + bitnum = 1 + self.options['data_bits'] elif state == 'GET STOP BITS': - bitnum = 1 + self.options['num_data_bits'] - bitnum += 0 if self.options['parity_type'] == 'none' else 1 + bitnum = 1 + self.options['data_bits'] + bitnum += 0 if self.options['parity'] == 'none' else 1 want_num = ceil(self.get_sample_point(rxtx, bitnum)) return {'skip': want_num - self.samplenum} + def get_idle_cond(self, rxtx, inv): + # Return a condition that corresponds to the (expected) end of + # the next frame, assuming that it will be an "idle frame" + # (constant high input level for the frame's length). + if self.idle_start[rxtx] is None: + return None + end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count + if end_of_frame < self.samplenum: + return None + return {'skip': end_of_frame - self.samplenum} + def inspect_sample(self, rxtx, signal, inv): # Inspect a sample returned by .wait() for the specified UART line. if inv: @@ -461,13 +484,32 @@ class Decoder(srd.Decoder): self.handle_break(rxtx) self.break_start[rxtx] = None + def inspect_idle(self, rxtx, signal, inv): + # Check each edge and each period of stable input (either level). + # Can derive the "idle frame period has passed" condition. + if inv: + signal = not signal + if not signal: + # Low input, cease inspection. + self.idle_start[rxtx] = None + return + # High input, either just reached, or still stable. + if self.idle_start[rxtx] is None: + self.idle_start[rxtx] = self.samplenum + diff = self.samplenum - self.idle_start[rxtx] + if diff < self.frame_len_sample_count: + return + ss, es = self.idle_start[rxtx], self.samplenum + self.putpse(ss, es, ['IDLE', rxtx, 0]) + self.idle_start[rxtx] = self.samplenum + def decode(self): if not self.samplerate: raise SamplerateError('Cannot decode without samplerate.') has_pin = [self.has_channel(ch) for ch in (RX, TX)] - if has_pin == [False, False]: - raise ChannelError('Either TX or RX (or both) pins required.') + if not True in has_pin: + raise ChannelError('Need at least one of TX or RX pins.') opt = self.options inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] @@ -476,12 +518,14 @@ class Decoder(srd.Decoder): # Determine the number of samples for a complete frame's time span. # A period of low signal (at least) that long is a break condition. frame_samples = 1 # START - frame_samples += self.options['num_data_bits'] - frame_samples += 0 if self.options['parity_type'] == 'none' else 1 - frame_samples += self.options['num_stop_bits'] + frame_samples += self.options['data_bits'] + frame_samples += 0 if self.options['parity'] == 'none' else 1 + frame_samples += self.options['stop_bits'] frame_samples *= self.bit_width - self.break_min_sample_count = ceil(frame_samples) + self.frame_len_sample_count = ceil(frame_samples) + self.break_min_sample_count = self.frame_len_sample_count cond_edge_idx = [None] * len(has_pin) + cond_idle_idx = [None] * len(has_pin) while True: conds = [] @@ -490,17 +534,33 @@ class Decoder(srd.Decoder): conds.append(self.get_wait_cond(RX, inv[RX])) cond_edge_idx[RX] = len(conds) conds.append({RX: 'e'}) + cond_idle_idx[RX] = None + idle_cond = self.get_idle_cond(RX, inv[RX]) + if idle_cond: + cond_idle_idx[RX] = len(conds) + conds.append(idle_cond) if has_pin[TX]: cond_data_idx[TX] = len(conds) conds.append(self.get_wait_cond(TX, inv[TX])) cond_edge_idx[TX] = len(conds) conds.append({TX: 'e'}) + cond_idle_idx[TX] = None + idle_cond = self.get_idle_cond(TX, inv[TX]) + if idle_cond: + cond_idle_idx[TX] = len(conds) + conds.append(idle_cond) (rx, tx) = self.wait(conds) if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]: self.inspect_sample(RX, rx, inv[RX]) if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]: self.inspect_edge(RX, rx, inv[RX]) + self.inspect_idle(RX, rx, inv[RX]) + if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]: + self.inspect_idle(RX, rx, inv[RX]) if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]: self.inspect_sample(TX, tx, inv[TX]) if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]: self.inspect_edge(TX, tx, inv[TX]) + self.inspect_idle(TX, tx, inv[TX]) + if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]: + self.inspect_idle(TX, tx, inv[TX])