X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=f01cacece3e86b18274432a0ba1e4d87a7b0e4f2;hp=5a6dfc00ecb8ee7066c946eb010924eee54b378a;hb=84c1c0b52820af2418186ac3ecf93a5c6373a22e;hpb=3a1803b09807eafba04c5e9fb0110d1c0d9f0eaf diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 5a6dfc0..f01cace 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2011-2013 Uwe Hermann +## Copyright (C) 2011-2014 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -18,12 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# UART protocol decoder - import sigrokdecode as srd ''' -Protocol output format: +OUTPUT_PYTHON format: UART packet: [, , ] @@ -32,6 +30,7 @@ This is the list of s and their respective : - 'STARTBIT': The data is the (integer) value of the start bit (0/1). - 'DATA': The data is the (integer) value of the UART data. Valid values range from 0 to 512 (as the data can be up to 9 bits in size). + - 'DATABITS': List of data bits and their ss/es numbers. - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). @@ -79,44 +78,81 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['uart'] - probes = [ + probes = [] + optional_probes = [ # Allow specifying only one of the signals, e.g. if only one data # direction exists (or is relevant). {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, ] - optional_probes = [] - options = { - 'baudrate': ['Baud rate', 115200], - 'num_data_bits': ['Data bits', 8], # Valid: 5-9. - 'parity_type': ['Parity type', 'none'], - 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported? - 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5. - 'bit_order': ['Bit order', 'lsb-first'], - 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin + options = ( + {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, + {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, + 'values': (5, 6, 7, 8, 9)}, + {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', + 'values': ('none', 'odd', 'even', 'zero', 'one')}, + {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', + 'values': ('yes', 'no')}, + {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, + 'values': (0.0, 0.5, 1.0, 1.5)}, + {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', + 'values': ('lsb-first', 'msb-first')}, + {'id': 'format', 'desc': 'Data format', 'default': 'ascii', + 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, # TODO: Options to invert the signal(s). - } + ) annotations = [ - ['Data', 'UART data'], - ['Start bits', 'UART start bits'], - ['Parity bits', 'UART parity bits'], - ['Stop bits', 'UART stop bits'], - ['Warnings', 'Warnings'], + ['rx-data', 'RX data'], + ['tx-data', 'TX data'], + ['rx-start', 'RX start bits'], + ['tx-start', 'TX start bits'], + ['rx-parity-ok', 'RX parity OK bits'], + ['tx-parity-ok', 'TX parity OK bits'], + ['rx-parity-err', 'RX parity error bits'], + ['tx-parity-err', 'TX parity error bits'], + ['rx-stop', 'RX stop bits'], + ['tx-stop', 'TX stop bits'], + ['rx-warnings', 'RX warnings'], + ['tx-warnings', 'TX warnings'], + ['rx-data-bits', 'RX data bits'], + ['tx-data-bits', 'TX data bits'], ] + annotation_rows = ( + ('rx-data', 'RX', (0, 2, 4, 6, 8)), + ('rx-data-bits', 'RX bits', (12,)), + ('rx-warnings', 'RX warnings', (10,)), + ('tx-data', 'TX', (1, 3, 5, 7, 9)), + ('tx-data-bits', 'TX bits', (13,)), + ('tx-warnings', 'TX warnings', (11,)), + ) + binary = ( + ('rx', 'RX dump'), + ('tx', 'TX dump'), + ('rxtx', 'RX/TX dump'), + ) def putx(self, rxtx, data): s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data) + def putpx(self, rxtx, data): + s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) + self.put(s - halfbit, self.samplenum + halfbit, self.out_python, data) + def putg(self, data): s, halfbit = self.samplenum, int(self.bit_width / 2) self.put(s - halfbit, s + halfbit, self.out_ann, data) def putp(self, data): s, halfbit = self.samplenum, int(self.bit_width / 2) - self.put(s - halfbit, s + halfbit, self.out_proto, data) + self.put(s - halfbit, s + halfbit, self.out_python, data) + + def putbin(self, rxtx, data): + s, halfbit = self.startsample[rxtx], int(self.bit_width / 2) + self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data) def __init__(self, **kwargs): + self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] self.startbit = [-1, -1] @@ -128,18 +164,18 @@ class Decoder(srd.Decoder): self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] self.oldbit = [1, 1] self.oldpins = [1, 1] + self.databits = [[], []] - def start(self, metadata): - self.samplerate = metadata['samplerate'] - self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart') - self.out_ann = self.add(srd.OUTPUT_ANN, 'uart') - - # The width of one UART bit in number of samples. - self.bit_width = \ - float(self.samplerate) / float(self.options['baudrate']) + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_bin = self.register(srd.OUTPUT_BINARY) + self.out_ann = self.register(srd.OUTPUT_ANN) - def report(self): - pass + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value; + # The width of one UART bit in number of samples. + self.bit_width = float(self.samplerate) / float(self.options['baudrate']) # Return true if we reached the middle of the desired bit, false otherwise. def reached_bit(self, rxtx, bitnum): @@ -188,7 +224,7 @@ class Decoder(srd.Decoder): self.state[rxtx] = 'GET DATA BITS' self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) - self.putg([1, ['Start bit', 'Start', 'S']]) + self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) def get_data_bits(self, rxtx, signal): # Skip samples until we're in the middle of the desired data bit. @@ -211,6 +247,12 @@ class Decoder(srd.Decoder): raise Exception('Invalid bit order value: %s', self.options['bit_order']) + self.putg([rxtx + 12, ['%d' % signal]]) + + # Store individual data bits and their start/end samplenumbers. + s, halfbit = self.samplenum, int(self.bit_width / 2) + self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) + # Return here, unless we already received all data bits. if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: self.cur_data_bit[rxtx] += 1 @@ -218,23 +260,29 @@ class Decoder(srd.Decoder): self.state[rxtx] = 'GET PARITY BIT' - self.putp(['DATA', rxtx, self.databyte[rxtx]]) + self.putpx(rxtx, ['DATABITS', rxtx, self.databits[rxtx]]) + self.putpx(rxtx, ['DATA', rxtx, self.databyte[rxtx]]) - s = 'RX: ' if (rxtx == RX) else 'TX: ' b, f = self.databyte[rxtx], self.options['format'] if f == 'ascii': - self.putx(rxtx, [0, [s + chr(b)]]) + c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b + self.putx(rxtx, [rxtx, [c]]) elif f == 'dec': - self.putx(rxtx, [0, [s + str(b)]]) + self.putx(rxtx, [rxtx, [str(b)]]) elif f == 'hex': - self.putx(rxtx, [0, [s + hex(b)[2:]]]) + self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]]) elif f == 'oct': - self.putx(rxtx, [0, [s + oct(b)[2:]]]) + self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]]) elif f == 'bin': - self.putx(rxtx, [0, [s + bin(b)[2:]]]) + self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]]) else: raise Exception('Invalid data format option: %s' % f) + self.putbin(rxtx, (rxtx, bytes([b]))) + self.putbin(rxtx, (2, bytes([b]))) + + self.databits = [[], []] + def get_parity_bit(self, rxtx, signal): # If no parity is used/configured, skip to the next state immediately. if self.options['parity_type'] == 'none': @@ -252,11 +300,11 @@ class Decoder(srd.Decoder): if parity_ok(self.options['parity_type'], self.paritybit[rxtx], self.databyte[rxtx], self.options['num_data_bits']): self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) - self.putg([2, ['Parity bit', 'Parity', 'P']]) + self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) else: # TODO: Return expected/actual parity values. self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... - self.putg([4, ['Parity error', 'Parity err', 'PE']]) + self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): @@ -271,16 +319,17 @@ class Decoder(srd.Decoder): # Stop bits must be 1. If not, we report an error. if self.stopbit1[rxtx] != 1: self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) - self.putg([4, ['Frame error', 'Frame err', 'FE']]) + self.putg([rxtx + 8, ['Frame error', 'Frame err', 'FE']]) # TODO: Abort? Ignore the frame? Other? self.state[rxtx] = 'WAIT FOR START BIT' self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) - self.putg([3, ['Stop bit', 'Stop', 'T']]) + self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) def decode(self, ss, es, data): - # TODO: Either RX or TX could be omitted (optional probe). + if self.samplerate is None: + raise Exception("Cannot decode without samplerate.") for (self.samplenum, pins) in data: # Note: Ignoring identical samples here for performance reasons @@ -289,8 +338,17 @@ class Decoder(srd.Decoder): # continue self.oldpins, (rx, tx) = pins, pins + # Either RX or TX (but not both) can be omitted. + has_pin = [rx in (0, 1), tx in (0, 1)] + if has_pin == [False, False]: + raise Exception('Either TX or RX (or both) pins required.') + # State machine. for rxtx in (RX, TX): + # Don't try to handle RX (or TX) if not supplied. + if not has_pin[rxtx]: + continue + signal = rx if (rxtx == RX) else tx if self.state[rxtx] == 'WAIT FOR START BIT':