X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=e767699250ce0ff70a8b5ce495816542ae1c15b8;hp=00be94bdd1b50da1a501a8d066716c992305ab85;hb=4539e9ca58966ce3c9cad4801b16c315e86ace01;hpb=e0a0123d2f7f1039fe52f24591dff262b4f8935c
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 00be94b..e767699 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -14,22 +14,24 @@
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see .
##
import sigrokdecode as srd
+from math import floor, ceil
'''
-Protocol output format:
+OUTPUT_PYTHON format:
-UART packet:
-[, , ]
+Packet:
+[, , ]
-This is the list of s and their respective :
+This is the list of s and their respective values:
- 'STARTBIT': The data is the (integer) value of the start bit (0/1).
- - 'DATA': The data is the (integer) value of the UART data. Valid values
- range from 0 to 512 (as the data can be up to 9 bits in size).
+ - 'DATA': This is always a tuple containing two items:
+ - 1st item: the (integer) value of the UART data. Valid values
+ range from 0 to 511 (as the data can be up to 9 bits in size).
+ - 2nd item: the list of individual data bits and their ss/es numbers.
- 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
- 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
- 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
@@ -65,11 +67,15 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
return (ones % 2) == 1
elif parity_type == 'even':
return (ones % 2) == 0
- else:
- raise Exception('Invalid parity type: %d' % parity_type)
+
+class SamplerateError(Exception):
+ pass
+
+class ChannelError(Exception):
+ pass
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'uart'
name = 'UART'
longname = 'Universal Asynchronous Receiver/Transmitter'
@@ -77,75 +83,106 @@ class Decoder(srd.Decoder):
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
- probes = [
+ optional_channels = (
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
- ]
- optional_probes = []
- options = {
- 'baudrate': ['Baud rate', 115200],
- 'num_data_bits': ['Data bits', 8], # Valid: 5-9.
- 'parity_type': ['Parity type', 'none'],
- 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported?
- 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5.
- 'bit_order': ['Bit order', 'lsb-first'],
- 'format': ['Data format', 'ascii'], # ascii/dec/hex/oct/bin
- # TODO: Options to invert the signal(s).
- }
- annotations = [
- ['rx-data', 'UART RX data'],
- ['tx-data', 'UART TX data'],
- ['start-bits', 'UART start bits'],
- ['parity-bits', 'UART parity bits'],
- ['stop-bits', 'UART stop bits'],
- ['warnings', 'Warnings'],
- ]
+ )
+ options = (
+ {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
+ {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
+ 'values': (5, 6, 7, 8, 9)},
+ {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
+ 'values': ('none', 'odd', 'even', 'zero', 'one')},
+ {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes',
+ 'values': ('yes', 'no')},
+ {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
+ 'values': (0.0, 0.5, 1.0, 1.5)},
+ {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
+ 'values': ('lsb-first', 'msb-first')},
+ {'id': 'format', 'desc': 'Data format', 'default': 'hex',
+ 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
+ {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no',
+ 'values': ('yes', 'no')},
+ {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
+ 'values': ('yes', 'no')},
+ )
+ annotations = (
+ ('rx-data', 'RX data'),
+ ('tx-data', 'TX data'),
+ ('rx-start', 'RX start bits'),
+ ('tx-start', 'TX start bits'),
+ ('rx-parity-ok', 'RX parity OK bits'),
+ ('tx-parity-ok', 'TX parity OK bits'),
+ ('rx-parity-err', 'RX parity error bits'),
+ ('tx-parity-err', 'TX parity error bits'),
+ ('rx-stop', 'RX stop bits'),
+ ('tx-stop', 'TX stop bits'),
+ ('rx-warnings', 'RX warnings'),
+ ('tx-warnings', 'TX warnings'),
+ ('rx-data-bits', 'RX data bits'),
+ ('tx-data-bits', 'TX data bits'),
+ )
+ annotation_rows = (
+ ('rx-data', 'RX', (0, 2, 4, 6, 8)),
+ ('rx-data-bits', 'RX bits', (12,)),
+ ('rx-warnings', 'RX warnings', (10,)),
+ ('tx-data', 'TX', (1, 3, 5, 7, 9)),
+ ('tx-data-bits', 'TX bits', (13,)),
+ ('tx-warnings', 'TX warnings', (11,)),
+ )
binary = (
('rx', 'RX dump'),
('tx', 'TX dump'),
('rxtx', 'RX/TX dump'),
)
+ idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
def putx(self, rxtx, data):
- s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
- self.put(s - halfbit, self.samplenum + halfbit, self.out_ann, data)
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+
+ def putpx(self, rxtx, data):
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
def putg(self, data):
- s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_ann, data)
+ s, halfbit = self.samplenum, self.bit_width / 2.0
+ self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data)
def putp(self, data):
- s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ s, halfbit = self.samplenum, self.bit_width / 2.0
+ self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
def putbin(self, rxtx, data):
- s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
- self.put(s - halfbit, self.samplenum + halfbit, self.out_bin, data)
+ s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
- def __init__(self, **kwargs):
+ def __init__(self):
self.samplerate = None
self.samplenum = 0
self.frame_start = [-1, -1]
self.startbit = [-1, -1]
self.cur_data_bit = [0, 0]
- self.databyte = [0, 0]
+ self.datavalue = [0, 0]
self.paritybit = [-1, -1]
self.stopbit1 = [-1, -1]
self.startsample = [-1, -1]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
self.oldbit = [1, 1]
- self.oldpins = [1, 1]
+ self.oldpins = [-1, -1]
+ self.databits = [[], []]
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
- self.out_bin = self.register(srd.OUTPUT_BINARY)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
+ self.bw = (self.options['num_data_bits'] + 7) // 8
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
- self.samplerate = value;
+ self.samplerate = value
# The width of one UART bit in number of samples.
self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
@@ -154,7 +191,9 @@ class Decoder(srd.Decoder):
# bitpos is the samplenumber which is in the middle of the
# specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
# (if used) or the first stop bit, and so on).
- bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0)
+ # The samples within bit are 0, 1, ..., (bit_width - 1), therefore
+ # index of the middle sample within bit window is (bit_width - 1) / 2.
+ bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0
bitpos += bitnum * self.bit_width
if self.samplenum >= bitpos:
return True
@@ -184,19 +223,22 @@ class Decoder(srd.Decoder):
self.startbit[rxtx] = signal
- # The startbit must be 0. If not, we report an error.
+ # The startbit must be 0. If not, we report an error and wait
+ # for the next start bit (assuming this one was spurious).
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
- # TODO: Abort? Ignore rest of the frame?
+ self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.state[rxtx] = 'WAIT FOR START BIT'
+ return
self.cur_data_bit[rxtx] = 0
- self.databyte[rxtx] = 0
+ self.datavalue[rxtx] = 0
self.startsample[rxtx] = -1
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([2, ['Start bit', 'Start', 'S']])
+ self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
@@ -209,15 +251,18 @@ class Decoder(srd.Decoder):
# Get the next data bit in LSB-first or MSB-first fashion.
if self.options['bit_order'] == 'lsb-first':
- self.databyte[rxtx] >>= 1
- self.databyte[rxtx] |= \
+ self.datavalue[rxtx] >>= 1
+ self.datavalue[rxtx] |= \
(signal << (self.options['num_data_bits'] - 1))
- elif self.options['bit_order'] == 'msb-first':
- self.databyte[rxtx] <<= 1
- self.databyte[rxtx] |= (signal << 0)
else:
- raise Exception('Invalid bit order value: %s',
- self.options['bit_order'])
+ self.datavalue[rxtx] <<= 1
+ self.datavalue[rxtx] |= (signal << 0)
+
+ self.putg([rxtx + 12, ['%d' % signal]])
+
+ # Store individual data bits and their start/end samplenumbers.
+ s, halfbit = self.samplenum, int(self.bit_width / 2)
+ self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
# Return here, unless we already received all data bits.
if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
@@ -226,25 +271,61 @@ class Decoder(srd.Decoder):
self.state[rxtx] = 'GET PARITY BIT'
- self.putp(['DATA', rxtx, self.databyte[rxtx]])
-
- b, f = self.databyte[rxtx], self.options['format']
- if f == 'ascii':
- c = chr(b) if b in range(30, 126 + 1) else '[%02X]' % b
- self.putx(rxtx, [rxtx, [c]])
- elif f == 'dec':
- self.putx(rxtx, [rxtx, [str(b)]])
- elif f == 'hex':
- self.putx(rxtx, [rxtx, [hex(b)[2:].zfill(2).upper()]])
- elif f == 'oct':
- self.putx(rxtx, [rxtx, [oct(b)[2:].zfill(3)]])
- elif f == 'bin':
- self.putx(rxtx, [rxtx, [bin(b)[2:].zfill(8)]])
+ self.putpx(rxtx, ['DATA', rxtx,
+ (self.datavalue[rxtx], self.databits[rxtx])])
+
+ b = self.datavalue[rxtx]
+ formatted = self.format_value(b)
+ if formatted is not None:
+ self.putx(rxtx, [rxtx, [formatted]])
+
+ bdata = b.to_bytes(self.bw, byteorder='big')
+ self.putbin(rxtx, [rxtx, bdata])
+ self.putbin(rxtx, [2, bdata])
+
+ self.databits[rxtx] = []
+
+ def format_value(self, v):
+ # Format value 'v' according to configured options.
+ # Reflects the user selected kind of representation, as well as
+ # the number of data bits in the UART frames.
+
+ fmt, bits = self.options['format'], self.options['num_data_bits']
+
+ # Assume "is printable" for values from 32 to including 126,
+ # below 32 is "control" and thus not printable, above 127 is
+ # "not ASCII" in its strict sense, 127 (DEL) is not printable,
+ # fall back to hex representation for non-printables.
+ if fmt == 'ascii':
+ if v in range(32, 126 + 1):
+ return chr(v)
+ hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]"
+ return hexfmt.format(v)
+
+ # Mere number to text conversion without prefix and padding
+ # for the "decimal" output format.
+ if fmt == 'dec':
+ return "{:d}".format(v)
+
+ # Padding with leading zeroes for hex/oct/bin formats, but
+ # without a prefix for density -- since the format is user
+ # specified, there is no ambiguity.
+ if fmt == 'hex':
+ digits = (bits + 4 - 1) // 4
+ fmtchar = "X"
+ elif fmt == 'oct':
+ digits = (bits + 3 - 1) // 3
+ fmtchar = "o"
+ elif fmt == 'bin':
+ digits = bits
+ fmtchar = "b"
else:
- raise Exception('Invalid data format option: %s' % f)
+ fmtchar = None
+ if fmtchar is not None:
+ fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar)
+ return fmt.format(v)
- self.putbin(rxtx, (rxtx, bytes([b])))
- self.putbin(rxtx, (2, bytes([b])))
+ return None
def get_parity_bit(self, rxtx, signal):
# If no parity is used/configured, skip to the next state immediately.
@@ -261,13 +342,13 @@ class Decoder(srd.Decoder):
self.state[rxtx] = 'GET STOP BITS'
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
- self.databyte[rxtx], self.options['num_data_bits']):
+ self.datavalue[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([3, ['Parity bit', 'Parity', 'P']])
+ self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([5, ['Parity error', 'Parity err', 'PE']])
+ self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
@@ -282,28 +363,43 @@ class Decoder(srd.Decoder):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([5, ['Frame error', 'Frame err', 'FE']])
+ self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([4, ['Stop bit', 'Stop', 'T']])
+ self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
- if self.samplerate is None:
- raise Exception("Cannot decode without samplerate.")
- # TODO: Either RX or TX could be omitted (optional probe).
+ if not self.samplerate:
+ raise SamplerateError('Cannot decode without samplerate.')
for (self.samplenum, pins) in data:
- # Note: Ignoring identical samples here for performance reasons
- # is not possible for this PD, at least not in the current state.
- # if self.oldpins == pins:
- # continue
+ # We want to skip identical samples for performance reasons but,
+ # for now, we can only do that when we are in the idle state
+ # (meaning both channels are waiting for the start bit).
+ if self.state == self.idle_state and self.oldpins == pins:
+ continue
+
self.oldpins, (rx, tx) = pins, pins
+ if self.options['invert_rx'] == 'yes':
+ rx = not rx
+ if self.options['invert_tx'] == 'yes':
+ tx = not tx
+
+ # Either RX or TX (but not both) can be omitted.
+ has_pin = [rx in (0, 1), tx in (0, 1)]
+ if has_pin == [False, False]:
+ raise ChannelError('Either TX or RX (or both) pins required.')
+
# State machine.
for rxtx in (RX, TX):
+ # Don't try to handle RX (or TX) if not supplied.
+ if not has_pin[rxtx]:
+ continue
+
signal = rx if (rxtx == RX) else tx
if self.state[rxtx] == 'WAIT FOR START BIT':
@@ -316,9 +412,6 @@ class Decoder(srd.Decoder):
self.get_parity_bit(rxtx, signal)
elif self.state[rxtx] == 'GET STOP BITS':
self.get_stop_bits(rxtx, signal)
- else:
- raise Exception('Invalid state: %s' % self.state[rxtx])
# Save current RX/TX values for the next round.
self.oldbit[rxtx] = signal
-