X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=da5e3033b3023cce80f8416ac96b580815d80eb0;hp=57031d73040643565cd6a6d5766bbc9058d3f0af;hb=21cda9512f29947617da45822ab524b1f76f56c1;hpb=6a15597a7b3f901b566b7bfc8c484a14e0fb6a11

diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 57031d7..da5e303 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -23,10 +23,10 @@ import sigrokdecode as srd
 '''
 OUTPUT_PYTHON format:
 
-UART packet:
-[<packet-type>, <rxtx>, <packet-data>]
+Packet:
+[<ptype>, <rxtx>, <pdata>]
 
-This is the list of <packet-type>s and their respective <packet-data>:
+This is the list of <ptype>s and their respective <pdata> values:
  - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
  - 'DATA': The data is the (integer) value of the UART data. Valid values
    range from 0 to 512 (as the data can be up to 9 bits in size).
@@ -69,8 +69,11 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
     else:
         raise Exception('Invalid parity type: %d' % parity_type)
 
+class SamplerateError(Exception):
+    pass
+
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'uart'
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter'
@@ -327,8 +330,8 @@ class Decoder(srd.Decoder):
         self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
 
     def decode(self, ss, es, data):
-        if self.samplerate is None:
-            raise Exception("Cannot decode without samplerate.")
+        if not self.samplerate:
+            raise SamplerateError('Cannot decode without samplerate.')
         for (self.samplenum, pins) in data:
 
             # Note: Ignoring identical samples here for performance reasons
@@ -360,8 +363,6 @@ class Decoder(srd.Decoder):
                     self.get_parity_bit(rxtx, signal)
                 elif self.state[rxtx] == 'GET STOP BITS':
                     self.get_stop_bits(rxtx, signal)
-                else:
-                    raise Exception('Invalid state: %s' % self.state[rxtx])
 
                 # Save current RX/TX values for the next round.
                 self.oldbit[rxtx] = signal