X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=6c3d85cf9b06c9f30db1d59c33aeab85b9ecb631;hp=08cb06600f13f5caff23e677d87cf4515107e0ea;hb=5166b0317835b35d810506f36e1a957e58109515;hpb=50bd5d259677faf87bb3408e111d0e833d7ba9b4 diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py index 08cb066..6c3d85c 100644 --- a/decoders/uart/pd.py +++ b/decoders/uart/pd.py @@ -1,7 +1,7 @@ ## ## This file is part of the libsigrokdecode project. ## -## Copyright (C) 2011-2012 Uwe Hermann +## Copyright (C) 2011-2014 Uwe Hermann ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,25 +14,40 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## -# UART protocol decoder - import sigrokdecode as srd +from common.srdhelper import bitpack +from math import floor, ceil + +''' +OUTPUT_PYTHON format: + +Packet: +[, , ] + +This is the list of s and their respective values: + - 'STARTBIT': The data is the (integer) value of the start bit (0/1). + - 'DATA': This is always a tuple containing two items: + - 1st item: the (integer) value of the UART data. Valid values + range from 0 to 511 (as the data can be up to 9 bits in size). + - 2nd item: the list of individual data bits and their ss/es numbers. + - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1). + - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1). + - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1). + - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1). + - 'PARITY ERROR': The data is a tuple with two entries. The first one is + the expected parity value, the second is the actual parity value. + - TODO: Frame error? + +The field is 0 for RX packets, 1 for TX packets. +''' # Used for differentiating between the two data directions. RX = 0 TX = 1 -# Annotation feed formats -ANN_ASCII = 0 -ANN_DEC = 1 -ANN_HEX = 2 -ANN_OCT = 3 -ANN_BITS = 4 - # Given a parity type to check (odd, even, zero, one), the value of the # parity bit, the value of the data, and the length of the data (5-9 bits, # usually 8 bits) return True if the parity is correct, False otherwise. @@ -53,11 +68,15 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits): return (ones % 2) == 1 elif parity_type == 'even': return (ones % 2) == 0 - else: - raise Exception('Invalid parity type: %d' % parity_type) + +class SamplerateError(Exception): + pass + +class ChannelError(Exception): + pass class Decoder(srd.Decoder): - api_version = 1 + api_version = 3 id = 'uart' name = 'UART' longname = 'Universal Asynchronous Receiver/Transmitter' @@ -65,240 +84,317 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['uart'] - probes = [ + optional_channels = ( # Allow specifying only one of the signals, e.g. if only one data # direction exists (or is relevant). {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'}, {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'}, - ] - optional_probes = [] - options = { - 'baudrate': ['Baud rate', 115200], - 'num_data_bits': ['Data bits', 8], # Valid: 5-9. - 'parity_type': ['Parity type', 'none'], - 'parity_check': ['Check parity?', 'yes'], # TODO: Bool supported? - 'num_stop_bits': ['Stop bit(s)', '1'], # String! 0, 0.5, 1, 1.5. - 'bit_order': ['Bit order', 'lsb-first'], - # TODO: Options to invert the signal(s). - } - annotations = [ - ['ASCII', 'Data bytes as ASCII characters'], - ['Decimal', 'Databytes as decimal, integer values'], - ['Hex', 'Data bytes in hex format'], - ['Octal', 'Data bytes as octal numbers'], - ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'], - ] + ) + options = ( + {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200}, + {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8, + 'values': (5, 6, 7, 8, 9)}, + {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none', + 'values': ('none', 'odd', 'even', 'zero', 'one')}, + {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes', + 'values': ('yes', 'no')}, + {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0, + 'values': (0.0, 0.5, 1.0, 1.5)}, + {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first', + 'values': ('lsb-first', 'msb-first')}, + {'id': 'format', 'desc': 'Data format', 'default': 'hex', + 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')}, + {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no', + 'values': ('yes', 'no')}, + {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no', + 'values': ('yes', 'no')}, + ) + annotations = ( + ('rx-data', 'RX data'), + ('tx-data', 'TX data'), + ('rx-start', 'RX start bits'), + ('tx-start', 'TX start bits'), + ('rx-parity-ok', 'RX parity OK bits'), + ('tx-parity-ok', 'TX parity OK bits'), + ('rx-parity-err', 'RX parity error bits'), + ('tx-parity-err', 'TX parity error bits'), + ('rx-stop', 'RX stop bits'), + ('tx-stop', 'TX stop bits'), + ('rx-warnings', 'RX warnings'), + ('tx-warnings', 'TX warnings'), + ('rx-data-bits', 'RX data bits'), + ('tx-data-bits', 'TX data bits'), + ) + annotation_rows = ( + ('rx-data', 'RX', (0, 2, 4, 6, 8)), + ('rx-data-bits', 'RX bits', (12,)), + ('rx-warnings', 'RX warnings', (10,)), + ('tx-data', 'TX', (1, 3, 5, 7, 9)), + ('tx-data-bits', 'TX bits', (13,)), + ('tx-warnings', 'TX warnings', (11,)), + ) + binary = ( + ('rx', 'RX dump'), + ('tx', 'TX dump'), + ('rxtx', 'RX/TX dump'), + ) + idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] def putx(self, rxtx, data): - self.put(self.startsample[rxtx], self.samplenum - 1, self.out_ann, data) + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data) + + def putpx(self, rxtx, data): + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data) - def __init__(self, **kwargs): + def putg(self, data): + s, halfbit = self.samplenum, self.bit_width / 2.0 + self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data) + + def putp(self, data): + s, halfbit = self.samplenum, self.bit_width / 2.0 + self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data) + + def putbin(self, rxtx, data): + s, halfbit = self.startsample[rxtx], self.bit_width / 2.0 + self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data) + + def __init__(self): + self.reset() + + def reset(self): + self.samplerate = None self.samplenum = 0 self.frame_start = [-1, -1] self.startbit = [-1, -1] self.cur_data_bit = [0, 0] - self.databyte = [0, 0] + self.datavalue = [0, 0] self.paritybit = [-1, -1] self.stopbit1 = [-1, -1] self.startsample = [-1, -1] self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT'] - self.oldbit = [None, None] - self.oldpins = None - - def start(self, metadata): - self.samplerate = metadata['samplerate'] - self.out_proto = self.add(srd.OUTPUT_PROTO, 'uart') - self.out_ann = self.add(srd.OUTPUT_ANN, 'uart') - - # The width of one UART bit in number of samples. - self.bit_width = \ - float(self.samplerate) / float(self.options['baudrate']) - - def report(self): - pass - - # Return true if we reached the middle of the desired bit, false otherwise. - def reached_bit(self, rxtx, bitnum): + self.databits = [[], []] + + def start(self): + self.out_python = self.register(srd.OUTPUT_PYTHON) + self.out_binary = self.register(srd.OUTPUT_BINARY) + self.out_ann = self.register(srd.OUTPUT_ANN) + self.bw = (self.options['num_data_bits'] + 7) // 8 + + def metadata(self, key, value): + if key == srd.SRD_CONF_SAMPLERATE: + self.samplerate = value + # The width of one UART bit in number of samples. + self.bit_width = float(self.samplerate) / float(self.options['baudrate']) + + def get_sample_point(self, rxtx, bitnum): + # Determine absolute sample number of a bit slot's sample point. # bitpos is the samplenumber which is in the middle of the # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit # (if used) or the first stop bit, and so on). - bitpos = self.frame_start[rxtx] + (self.bit_width / 2.0) + # The samples within bit are 0, 1, ..., (bit_width - 1), therefore + # index of the middle sample within bit window is (bit_width - 1) / 2. + bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0 bitpos += bitnum * self.bit_width - if self.samplenum >= bitpos: - return True - return False - - def reached_bit_last(self, rxtx, bitnum): - bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width) - if self.samplenum >= bitpos: - return True - return False - - def wait_for_start_bit(self, rxtx, old_signal, signal): - # The start bit is always 0 (low). As the idle UART (and the stop bit) - # level is 1 (high), the beginning of a start bit is a falling edge. - if not (old_signal == 1 and signal == 0): - return + return bitpos + def wait_for_start_bit(self, rxtx, signal): # Save the sample number where the start bit begins. self.frame_start[rxtx] = self.samplenum self.state[rxtx] = 'GET START BIT' def get_start_bit(self, rxtx, signal): - # Skip samples until we're in the middle of the start bit. - if not self.reached_bit(rxtx, 0): - return - self.startbit[rxtx] = signal - # The startbit must be 0. If not, we report an error. + # The startbit must be 0. If not, we report an error and wait + # for the next start bit (assuming this one was spurious). if self.startbit[rxtx] != 0: - self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - ['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) - # TODO: Abort? Ignore rest of the frame? + self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]]) + self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) + self.state[rxtx] = 'WAIT FOR START BIT' + return self.cur_data_bit[rxtx] = 0 - self.databyte[rxtx] = 0 + self.datavalue[rxtx] = 0 self.startsample[rxtx] = -1 - self.state[rxtx] = 'GET DATA BITS' + self.putp(['STARTBIT', rxtx, self.startbit[rxtx]]) + self.putg([rxtx + 2, ['Start bit', 'Start', 'S']]) - self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - ['STARTBIT', rxtx, self.startbit[rxtx]]) - self.put(self.frame_start[rxtx], self.samplenum, self.out_ann, - [ANN_ASCII, ['Start bit', 'Start', 'S']]) + self.state[rxtx] = 'GET DATA BITS' def get_data_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the desired data bit. - if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1): - return - - # Save the sample number where the data byte starts. + # Save the sample number of the middle of the first data bit. if self.startsample[rxtx] == -1: self.startsample[rxtx] = self.samplenum - # Get the next data bit in LSB-first or MSB-first fashion. - if self.options['bit_order'] == 'lsb-first': - self.databyte[rxtx] >>= 1 - self.databyte[rxtx] |= \ - (signal << (self.options['num_data_bits'] - 1)) - elif self.options['bit_order'] == 'msb-first': - self.databyte[rxtx] <<= 1 - self.databyte[rxtx] |= (signal << 0) - else: - raise Exception('Invalid bit order value: %s', - self.options['bit_order']) + self.putg([rxtx + 12, ['%d' % signal]]) + + # Store individual data bits and their start/end samplenumbers. + s, halfbit = self.samplenum, int(self.bit_width / 2) + self.databits[rxtx].append([signal, s - halfbit, s + halfbit]) # Return here, unless we already received all data bits. - # TODO? Off-by-one? - if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1: - self.cur_data_bit[rxtx] += 1 + self.cur_data_bit[rxtx] += 1 + if self.cur_data_bit[rxtx] < self.options['num_data_bits']: return - self.state[rxtx] = 'GET PARITY BIT' + # Convert accumulated data bits to a data value. + bits = [b[0] for b in self.databits[rxtx]] + if self.options['bit_order'] == 'msb-first': + bits.reverse() + self.datavalue[rxtx] = bitpack(bits) + self.putpx(rxtx, ['DATA', rxtx, + (self.datavalue[rxtx], self.databits[rxtx])]) - self.put(self.startsample[rxtx], self.samplenum - 1, self.out_proto, - ['DATA', rxtx, self.databyte[rxtx]]) + b = self.datavalue[rxtx] + formatted = self.format_value(b) + if formatted is not None: + self.putx(rxtx, [rxtx, [formatted]]) - s = 'RX: ' if (rxtx == RX) else 'TX: ' - self.putx(rxtx, [ANN_ASCII, [s + chr(self.databyte[rxtx])]]) - self.putx(rxtx, [ANN_DEC, [s + str(self.databyte[rxtx])]]) - self.putx(rxtx, [ANN_HEX, [s + hex(self.databyte[rxtx]), - s + hex(self.databyte[rxtx])[2:]]]) - self.putx(rxtx, [ANN_OCT, [s + oct(self.databyte[rxtx]), - s + oct(self.databyte[rxtx])[2:]]]) - self.putx(rxtx, [ANN_BITS, [s + bin(self.databyte[rxtx]), - s + bin(self.databyte[rxtx])[2:]]]) + bdata = b.to_bytes(self.bw, byteorder='big') + self.putbin(rxtx, [rxtx, bdata]) + self.putbin(rxtx, [2, bdata]) - def get_parity_bit(self, rxtx, signal): - # If no parity is used/configured, skip to the next state immediately. + self.databits[rxtx] = [] + + # Advance to either reception of the parity bit, or reception of + # the STOP bits if parity is not applicable. + self.state[rxtx] = 'GET PARITY BIT' if self.options['parity_type'] == 'none': self.state[rxtx] = 'GET STOP BITS' - return - # Skip samples until we're in the middle of the parity bit. - if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1): - return + def format_value(self, v): + # Format value 'v' according to configured options. + # Reflects the user selected kind of representation, as well as + # the number of data bits in the UART frames. + + fmt, bits = self.options['format'], self.options['num_data_bits'] + + # Assume "is printable" for values from 32 to including 126, + # below 32 is "control" and thus not printable, above 127 is + # "not ASCII" in its strict sense, 127 (DEL) is not printable, + # fall back to hex representation for non-printables. + if fmt == 'ascii': + if v in range(32, 126 + 1): + return chr(v) + hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]" + return hexfmt.format(v) + + # Mere number to text conversion without prefix and padding + # for the "decimal" output format. + if fmt == 'dec': + return "{:d}".format(v) + + # Padding with leading zeroes for hex/oct/bin formats, but + # without a prefix for density -- since the format is user + # specified, there is no ambiguity. + if fmt == 'hex': + digits = (bits + 4 - 1) // 4 + fmtchar = "X" + elif fmt == 'oct': + digits = (bits + 3 - 1) // 3 + fmtchar = "o" + elif fmt == 'bin': + digits = bits + fmtchar = "b" + else: + fmtchar = None + if fmtchar is not None: + fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar) + return fmt.format(v) - self.paritybit[rxtx] = signal + return None - self.state[rxtx] = 'GET STOP BITS' + def get_parity_bit(self, rxtx, signal): + self.paritybit[rxtx] = signal if parity_ok(self.options['parity_type'], self.paritybit[rxtx], - self.databyte[rxtx], self.options['num_data_bits']): - # TODO: Fix range. - self.put(self.samplenum, self.samplenum, self.out_proto, - ['PARITYBIT', rxtx, self.paritybit[rxtx]]) - self.put(self.samplenum, self.samplenum, self.out_ann, - [ANN_ASCII, ['Parity bit', 'Parity', 'P']]) + self.datavalue[rxtx], self.options['num_data_bits']): + self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]]) + self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']]) else: - # TODO: Fix range. # TODO: Return expected/actual parity values. - self.put(self.samplenum, self.samplenum, self.out_proto, - ['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... - self.put(self.samplenum, self.samplenum, self.out_ann, - [ANN_ASCII, ['Parity error', 'Parity err', 'PE']]) + self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple... + self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']]) + + self.state[rxtx] = 'GET STOP BITS' # TODO: Currently only supports 1 stop bit. def get_stop_bits(self, rxtx, signal): - # Skip samples until we're in the middle of the stop bit(s). - skip_parity = 0 if self.options['parity_type'] == 'none' else 1 - b = self.options['num_data_bits'] + 1 + skip_parity - if not self.reached_bit(rxtx, b): - return - self.stopbit1[rxtx] = signal # Stop bits must be 1. If not, we report an error. if self.stopbit1[rxtx] != 1: - self.put(self.frame_start[rxtx], self.samplenum, self.out_proto, - ['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) + self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]]) + self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']]) # TODO: Abort? Ignore the frame? Other? - self.state[rxtx] = 'WAIT FOR START BIT' + self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]]) + self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']]) - # TODO: Fix range. - self.put(self.samplenum, self.samplenum, self.out_proto, - ['STOPBIT', rxtx, self.stopbit1[rxtx]]) - self.put(self.samplenum, self.samplenum, self.out_ann, - [ANN_ASCII, ['Stop bit', 'Stop', 'P']]) - - def decode(self, ss, es, data): - # TODO: Either RX or TX could be omitted (optional probe). - for (self.samplenum, pins) in data: - - # Note: Ignoring identical samples here for performance reasons - # is not possible for this PD, at least not in the current state. - # if self.oldpins == pins: - # continue - self.oldpins, (rx, tx) = pins, pins - - # First sample: Save RX/TX value. - if self.oldbit[RX] == None: - self.oldbit[RX] = rx - continue - if self.oldbit[TX] == None: - self.oldbit[TX] = tx - continue - - # State machine. - for rxtx in (RX, TX): - signal = rx if (rxtx == RX) else tx - - if self.state[rxtx] == 'WAIT FOR START BIT': - self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal) - elif self.state[rxtx] == 'GET START BIT': - self.get_start_bit(rxtx, signal) - elif self.state[rxtx] == 'GET DATA BITS': - self.get_data_bits(rxtx, signal) - elif self.state[rxtx] == 'GET PARITY BIT': - self.get_parity_bit(rxtx, signal) - elif self.state[rxtx] == 'GET STOP BITS': - self.get_stop_bits(rxtx, signal) - else: - raise Exception('Invalid state: %s' % self.state[rxtx]) - - # Save current RX/TX values for the next round. - self.oldbit[rxtx] = signal + self.state[rxtx] = 'WAIT FOR START BIT' + def get_wait_cond(self, rxtx, inv): + # Return condititions that are suitable for Decoder.wait(). Those + # conditions either match the falling edge of the START bit, or + # the sample point of the next bit time. + state = self.state[rxtx] + if state == 'WAIT FOR START BIT': + return {rxtx: 'r' if inv else 'f'} + if state == 'GET START BIT': + bitnum = 0 + elif state == 'GET DATA BITS': + bitnum = 1 + self.cur_data_bit[rxtx] + elif state == 'GET PARITY BIT': + bitnum = 1 + self.options['num_data_bits'] + elif state == 'GET STOP BITS': + bitnum = 1 + self.options['num_data_bits'] + bitnum += 0 if self.options['parity_type'] == 'none' else 1 + want_num = ceil(self.get_sample_point(rxtx, bitnum)) + return {'skip': want_num - self.samplenum} + + def inspect_sample(self, rxtx, signal, inv): + # Inspect a sample returned by .wait() for the specified UART line. + if inv: + signal = not signal + + state = self.state[rxtx] + if state == 'WAIT FOR START BIT': + self.wait_for_start_bit(rxtx, signal) + elif state == 'GET START BIT': + self.get_start_bit(rxtx, signal) + elif state == 'GET DATA BITS': + self.get_data_bits(rxtx, signal) + elif state == 'GET PARITY BIT': + self.get_parity_bit(rxtx, signal) + elif state == 'GET STOP BITS': + self.get_stop_bits(rxtx, signal) + + def decode(self): + if not self.samplerate: + raise SamplerateError('Cannot decode without samplerate.') + + has_pin = [self.has_channel(ch) for ch in (RX, TX)] + if has_pin == [False, False]: + raise ChannelError('Either TX or RX (or both) pins required.') + + opt = self.options + inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes'] + cond_idx = [None] * len(has_pin) + + while True: + conds = [] + if has_pin[RX]: + cond_idx[RX] = len(conds) + conds.append(self.get_wait_cond(RX, inv[RX])) + if has_pin[TX]: + cond_idx[TX] = len(conds) + conds.append(self.get_wait_cond(TX, inv[TX])) + (rx, tx) = self.wait(conds) + if cond_idx[RX] is not None and self.matched[cond_idx[RX]]: + self.inspect_sample(RX, rx, inv[RX]) + if cond_idx[TX] is not None and self.matched[cond_idx[TX]]: + self.inspect_sample(TX, tx, inv[TX])