X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fuart%2Fpd.py;h=67f4c7e702760e3d76f92695c58de08bf3719564;hp=6bba65306c6e022b2162e5b4480c96424d43108b;hb=c69e72bc8d3524140959157fb605b7dd53b40af4;hpb=98b8913915e8649cca83f543e84fbf128707b5fb
diff --git a/decoders/uart/pd.py b/decoders/uart/pd.py
index 6bba653..67f4c7e 100644
--- a/decoders/uart/pd.py
+++ b/decoders/uart/pd.py
@@ -14,11 +14,11 @@
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see .
##
import sigrokdecode as srd
+from common.srdhelper import bitpack
from math import floor, ceil
'''
@@ -39,7 +39,11 @@ This is the list of s and their respective values:
- 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
- 'PARITY ERROR': The data is a tuple with two entries. The first one is
the expected parity value, the second is the actual parity value.
- - TODO: Frame error?
+ - 'BREAK': The data is always 0.
+ - 'FRAME': The data is always a tuple containing two items: The (integer)
+ value of the UART data, and a boolean which reflects the validity of the
+ UART frame.
+ - 'IDLE': The data is always 0.
The field is 0 for RX packets, 1 for TX packets.
'''
@@ -52,7 +56,10 @@ TX = 1
# parity bit, the value of the data, and the length of the data (5-9 bits,
# usually 8 bits) return True if the parity is correct, False otherwise.
# 'none' is _not_ allowed as value for 'parity_type'.
-def parity_ok(parity_type, parity_bit, data, num_data_bits):
+def parity_ok(parity_type, parity_bit, data, data_bits):
+
+ if parity_type == 'ignore':
+ return True
# Handle easy cases first (parity bit is always 1 or 0).
if parity_type == 'zero':
@@ -75,8 +82,14 @@ class SamplerateError(Exception):
class ChannelError(Exception):
pass
+class Ann:
+ RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
+ RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
+ RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
+ range(18)
+
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'uart'
name = 'UART'
longname = 'Universal Asynchronous Receiver/Transmitter'
@@ -84,6 +97,7 @@ class Decoder(srd.Decoder):
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
+ tags = ['Embedded/industrial']
optional_channels = (
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
@@ -92,22 +106,27 @@ class Decoder(srd.Decoder):
)
options = (
{'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
- {'id': 'num_data_bits', 'desc': 'Data bits', 'default': 8,
+ {'id': 'data_bits', 'desc': 'Data bits', 'default': 8,
'values': (5, 6, 7, 8, 9)},
- {'id': 'parity_type', 'desc': 'Parity type', 'default': 'none',
- 'values': ('none', 'odd', 'even', 'zero', 'one')},
- {'id': 'parity_check', 'desc': 'Check parity?', 'default': 'yes',
- 'values': ('yes', 'no')},
- {'id': 'num_stop_bits', 'desc': 'Stop bits', 'default': 1.0,
+ {'id': 'parity', 'desc': 'Parity', 'default': 'none',
+ 'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')},
+ {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0,
'values': (0.0, 0.5, 1.0, 1.5)},
{'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
'values': ('lsb-first', 'msb-first')},
- {'id': 'format', 'desc': 'Data format', 'default': 'ascii',
+ {'id': 'format', 'desc': 'Data format', 'default': 'hex',
'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
- {'id': 'invert_rx', 'desc': 'Invert RX?', 'default': 'no',
+ {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no',
'values': ('yes', 'no')},
- {'id': 'invert_tx', 'desc': 'Invert TX?', 'default': 'no',
+ {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
'values': ('yes', 'no')},
+ {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
+ {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
+ 'default': -1},
+ {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
+ 'default': -1},
+ {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
+ {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
)
annotations = (
('rx-data', 'RX data'),
@@ -124,14 +143,22 @@ class Decoder(srd.Decoder):
('tx-warnings', 'TX warnings'),
('rx-data-bits', 'RX data bits'),
('tx-data-bits', 'TX data bits'),
+ ('rx-break', 'RX break'),
+ ('tx-break', 'TX break'),
+ ('rx-packet', 'RX packet'),
+ ('tx-packet', 'TX packet'),
)
annotation_rows = (
- ('rx-data', 'RX', (0, 2, 4, 6, 8)),
- ('rx-data-bits', 'RX bits', (12,)),
- ('rx-warnings', 'RX warnings', (10,)),
- ('tx-data', 'TX', (1, 3, 5, 7, 9)),
- ('tx-data-bits', 'TX bits', (13,)),
- ('tx-warnings', 'TX warnings', (11,)),
+ ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
+ ('rx-data', 'RX', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
+ ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
+ ('rx-break', 'RX break', (Ann.RX_BREAK,)),
+ ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
+ ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
+ ('tx-data', 'TX', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
+ ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
+ ('tx-break', 'TX break', (Ann.TX_BREAK,)),
+ ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
)
binary = (
('rx', 'RX dump'),
@@ -144,6 +171,10 @@ class Decoder(srd.Decoder):
s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+ def putx_packet(self, rxtx, data):
+ s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
+ self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
+
def putpx(self, rxtx, data):
s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
@@ -156,14 +187,23 @@ class Decoder(srd.Decoder):
s, halfbit = self.samplenum, self.bit_width / 2.0
self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
+ def putgse(self, ss, es, data):
+ self.put(ss, es, self.out_ann, data)
+
+ def putpse(self, ss, es, data):
+ self.put(ss, es, self.out_python, data)
+
def putbin(self, rxtx, data):
s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
- self.samplenum = 0
self.frame_start = [-1, -1]
+ self.frame_valid = [None, None]
self.startbit = [-1, -1]
self.cur_data_bit = [0, 0]
self.datavalue = [0, 0]
@@ -171,15 +211,17 @@ class Decoder(srd.Decoder):
self.stopbit1 = [-1, -1]
self.startsample = [-1, -1]
self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
- self.oldbit = [1, 1]
- self.oldpins = [-1, -1]
self.databits = [[], []]
+ self.break_start = [None, None]
+ self.packet_cache = [[], []]
+ self.ss_packet, self.es_packet = [None, None], [None, None]
+ self.idle_start = [None, None]
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_binary = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
- self.bw = (self.options['num_data_bits'] + 7) // 8
+ self.bw = (self.options['data_bits'] + 7) // 8
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
@@ -187,48 +229,40 @@ class Decoder(srd.Decoder):
# The width of one UART bit in number of samples.
self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
- # Return true if we reached the middle of the desired bit, false otherwise.
- def reached_bit(self, rxtx, bitnum):
- # bitpos is the samplenumber which is in the middle of the
- # specified UART bit (0 = start bit, 1..x = data, x+1 = parity bit
- # (if used) or the first stop bit, and so on).
- # The samples within bit are 0, 1, ..., (bit_width - 1), therefore
- # index of the middle sample within bit window is (bit_width - 1) / 2.
- bitpos = self.frame_start[rxtx] + (self.bit_width - 1) / 2.0
+ def get_sample_point(self, rxtx, bitnum):
+ # Determine absolute sample number of a bit slot's sample point.
+ # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
+ # x+1 = parity bit (if used) or the first stop bit, and so on).
+ # Accept a position in the range of 1-99% of the full bit width.
+ # Assume 50% for invalid input specs for backwards compatibility.
+ perc = self.options['sample_point'] or 50
+ if not perc or perc not in range(1, 100):
+ perc = 50
+ perc /= 100.0
+ bitpos = (self.bit_width - 1) * perc
+ bitpos += self.frame_start[rxtx]
bitpos += bitnum * self.bit_width
- if self.samplenum >= bitpos:
- return True
- return False
-
- def reached_bit_last(self, rxtx, bitnum):
- bitpos = self.frame_start[rxtx] + ((bitnum + 1) * self.bit_width)
- if self.samplenum >= bitpos:
- return True
- return False
-
- def wait_for_start_bit(self, rxtx, old_signal, signal):
- # The start bit is always 0 (low). As the idle UART (and the stop bit)
- # level is 1 (high), the beginning of a start bit is a falling edge.
- if not (old_signal == 1 and signal == 0):
- return
+ return bitpos
+ def wait_for_start_bit(self, rxtx, signal):
# Save the sample number where the start bit begins.
self.frame_start[rxtx] = self.samplenum
+ self.frame_valid[rxtx] = True
self.state[rxtx] = 'GET START BIT'
def get_start_bit(self, rxtx, signal):
- # Skip samples until we're in the middle of the start bit.
- if not self.reached_bit(rxtx, 0):
- return
-
self.startbit[rxtx] = signal
# The startbit must be 0. If not, we report an error and wait
# for the next start bit (assuming this one was spurious).
if self.startbit[rxtx] != 0:
self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
+ self.frame_valid[rxtx] = False
+ es = self.samplenum + ceil(self.bit_width / 2.0)
+ self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
+ (self.datavalue[rxtx], self.frame_valid[rxtx])])
self.state[rxtx] = 'WAIT FOR START BIT'
return
@@ -236,42 +270,56 @@ class Decoder(srd.Decoder):
self.datavalue[rxtx] = 0
self.startsample[rxtx] = -1
- self.state[rxtx] = 'GET DATA BITS'
-
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
+ self.putg([Ann.RX_START + rxtx, ['Start bit', 'Start', 'S']])
- def get_data_bits(self, rxtx, signal):
- # Skip samples until we're in the middle of the desired data bit.
- if not self.reached_bit(rxtx, self.cur_data_bit[rxtx] + 1):
+ self.state[rxtx] = 'GET DATA BITS'
+
+ def handle_packet(self, rxtx):
+ d = 'rx' if (rxtx == RX) else 'tx'
+ delim = self.options[d + '_packet_delim']
+ plen = self.options[d + '_packet_len']
+ if delim == -1 and plen == -1:
return
+ # Cache data values until we see the delimiter and/or the specified
+ # packet length has been reached (whichever happens first).
+ if len(self.packet_cache[rxtx]) == 0:
+ self.ss_packet[rxtx] = self.startsample[rxtx]
+ self.packet_cache[rxtx].append(self.datavalue[rxtx])
+ if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
+ self.es_packet[rxtx] = self.samplenum
+ s = ''
+ for b in self.packet_cache[rxtx]:
+ s += self.format_value(b)
+ if self.options['format'] != 'ascii':
+ s += ' '
+ if self.options['format'] != 'ascii' and s[-1] == ' ':
+ s = s[:-1] # Drop trailing space.
+ self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
+ self.packet_cache[rxtx] = []
+
+ def get_data_bits(self, rxtx, signal):
# Save the sample number of the middle of the first data bit.
if self.startsample[rxtx] == -1:
self.startsample[rxtx] = self.samplenum
- # Get the next data bit in LSB-first or MSB-first fashion.
- if self.options['bit_order'] == 'lsb-first':
- self.datavalue[rxtx] >>= 1
- self.datavalue[rxtx] |= \
- (signal << (self.options['num_data_bits'] - 1))
- else:
- self.datavalue[rxtx] <<= 1
- self.datavalue[rxtx] |= (signal << 0)
-
- self.putg([rxtx + 12, ['%d' % signal]])
+ self.putg([Ann.RX_DATA_BIT + rxtx, ['%d' % signal]])
# Store individual data bits and their start/end samplenumbers.
s, halfbit = self.samplenum, int(self.bit_width / 2)
self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
# Return here, unless we already received all data bits.
- if self.cur_data_bit[rxtx] < self.options['num_data_bits'] - 1:
- self.cur_data_bit[rxtx] += 1
+ self.cur_data_bit[rxtx] += 1
+ if self.cur_data_bit[rxtx] < self.options['data_bits']:
return
- self.state[rxtx] = 'GET PARITY BIT'
-
+ # Convert accumulated data bits to a data value.
+ bits = [b[0] for b in self.databits[rxtx]]
+ if self.options['bit_order'] == 'msb-first':
+ bits.reverse()
+ self.datavalue[rxtx] = bitpack(bits)
self.putpx(rxtx, ['DATA', rxtx,
(self.datavalue[rxtx], self.databits[rxtx])])
@@ -284,14 +332,22 @@ class Decoder(srd.Decoder):
self.putbin(rxtx, [rxtx, bdata])
self.putbin(rxtx, [2, bdata])
+ self.handle_packet(rxtx)
+
self.databits[rxtx] = []
+ # Advance to either reception of the parity bit, or reception of
+ # the STOP bits if parity is not applicable.
+ self.state[rxtx] = 'GET PARITY BIT'
+ if self.options['parity'] == 'none':
+ self.state[rxtx] = 'GET STOP BITS'
+
def format_value(self, v):
# Format value 'v' according to configured options.
# Reflects the user selected kind of representation, as well as
# the number of data bits in the UART frames.
- fmt, bits = self.options['format'], self.options['num_data_bits']
+ fmt, bits = self.options['format'], self.options['data_bits']
# Assume "is printable" for values from 32 to including 126,
# below 32 is "control" and thus not printable, above 127 is
@@ -329,90 +385,188 @@ class Decoder(srd.Decoder):
return None
def get_parity_bit(self, rxtx, signal):
- # If no parity is used/configured, skip to the next state immediately.
- if self.options['parity_type'] == 'none':
- self.state[rxtx] = 'GET STOP BITS'
- return
-
- # Skip samples until we're in the middle of the parity bit.
- if not self.reached_bit(rxtx, self.options['num_data_bits'] + 1):
- return
-
self.paritybit[rxtx] = signal
- self.state[rxtx] = 'GET STOP BITS'
-
- if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
- self.datavalue[rxtx], self.options['num_data_bits']):
+ if parity_ok(self.options['parity'], self.paritybit[rxtx],
+ self.datavalue[rxtx], self.options['data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
+ self.putg([Ann.RX_PARITY_OK + rxtx, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([rxtx + 6, ['Parity error', 'Parity err', 'PE']])
+ self.putg([Ann.RX_PARITY_ERR + rxtx, ['Parity error', 'Parity err', 'PE']])
+ self.frame_valid[rxtx] = False
+
+ self.state[rxtx] = 'GET STOP BITS'
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
- # Skip samples until we're in the middle of the stop bit(s).
- skip_parity = 0 if self.options['parity_type'] == 'none' else 1
- b = self.options['num_data_bits'] + 1 + skip_parity
- if not self.reached_bit(rxtx, b):
- return
-
self.stopbit1[rxtx] = signal
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 10, ['Frame error', 'Frame err', 'FE']])
- # TODO: Abort? Ignore the frame? Other?
+ self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
+ self.frame_valid[rxtx] = False
+
+ self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
+ self.putg([Ann.RX_PARITY_OK + rxtx, ['Stop bit', 'Stop', 'T']])
+
+ # Pass the complete UART frame to upper layers.
+ es = self.samplenum + ceil(self.bit_width / 2.0)
+ self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
+ (self.datavalue[rxtx], self.frame_valid[rxtx])])
self.state[rxtx] = 'WAIT FOR START BIT'
+ self.idle_start[rxtx] = self.frame_start[rxtx] + self.frame_len_sample_count
- self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
+ def handle_break(self, rxtx):
+ self.putpse(self.frame_start[rxtx], self.samplenum,
+ ['BREAK', rxtx, 0])
+ self.putgse(self.frame_start[rxtx], self.samplenum,
+ [Ann.RX_BREAK + rxtx, ['Break condition', 'Break', 'Brk', 'B']])
+ self.state[rxtx] = 'WAIT FOR START BIT'
- def decode(self, ss, es, data):
+ def get_wait_cond(self, rxtx, inv):
+ # Return condititions that are suitable for Decoder.wait(). Those
+ # conditions either match the falling edge of the START bit, or
+ # the sample point of the next bit time.
+ state = self.state[rxtx]
+ if state == 'WAIT FOR START BIT':
+ return {rxtx: 'r' if inv else 'f'}
+ if state == 'GET START BIT':
+ bitnum = 0
+ elif state == 'GET DATA BITS':
+ bitnum = 1 + self.cur_data_bit[rxtx]
+ elif state == 'GET PARITY BIT':
+ bitnum = 1 + self.options['data_bits']
+ elif state == 'GET STOP BITS':
+ bitnum = 1 + self.options['data_bits']
+ bitnum += 0 if self.options['parity'] == 'none' else 1
+ want_num = ceil(self.get_sample_point(rxtx, bitnum))
+ return {'skip': want_num - self.samplenum}
+
+ def get_idle_cond(self, rxtx, inv):
+ # Return a condition that corresponds to the (expected) end of
+ # the next frame, assuming that it will be an "idle frame"
+ # (constant high input level for the frame's length).
+ if self.idle_start[rxtx] is None:
+ return None
+ end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count
+ if end_of_frame < self.samplenum:
+ return None
+ return {'skip': end_of_frame - self.samplenum}
+
+ def inspect_sample(self, rxtx, signal, inv):
+ # Inspect a sample returned by .wait() for the specified UART line.
+ if inv:
+ signal = not signal
+
+ state = self.state[rxtx]
+ if state == 'WAIT FOR START BIT':
+ self.wait_for_start_bit(rxtx, signal)
+ elif state == 'GET START BIT':
+ self.get_start_bit(rxtx, signal)
+ elif state == 'GET DATA BITS':
+ self.get_data_bits(rxtx, signal)
+ elif state == 'GET PARITY BIT':
+ self.get_parity_bit(rxtx, signal)
+ elif state == 'GET STOP BITS':
+ self.get_stop_bits(rxtx, signal)
+
+ def inspect_edge(self, rxtx, signal, inv):
+ # Inspect edges, independently from traffic, to detect break conditions.
+ if inv:
+ signal = not signal
+ if not signal:
+ # Signal went low. Start another interval.
+ self.break_start[rxtx] = self.samplenum
+ return
+ # Signal went high. Was there an extended period with low signal?
+ if self.break_start[rxtx] is None:
+ return
+ diff = self.samplenum - self.break_start[rxtx]
+ if diff >= self.break_min_sample_count:
+ self.handle_break(rxtx)
+ self.break_start[rxtx] = None
+
+ def inspect_idle(self, rxtx, signal, inv):
+ # Check each edge and each period of stable input (either level).
+ # Can derive the "idle frame period has passed" condition.
+ if inv:
+ signal = not signal
+ if not signal:
+ # Low input, cease inspection.
+ self.idle_start[rxtx] = None
+ return
+ # High input, either just reached, or still stable.
+ if self.idle_start[rxtx] is None:
+ self.idle_start[rxtx] = self.samplenum
+ diff = self.samplenum - self.idle_start[rxtx]
+ if diff < self.frame_len_sample_count:
+ return
+ ss, es = self.idle_start[rxtx], self.samplenum
+ self.putpse(ss, es, ['IDLE', rxtx, 0])
+ self.idle_start[rxtx] = self.samplenum
+
+ def decode(self):
if not self.samplerate:
raise SamplerateError('Cannot decode without samplerate.')
- for (self.samplenum, pins) in data:
-
- # We want to skip identical samples for performance reasons but,
- # for now, we can only do that when we are in the idle state
- # (meaning both channels are waiting for the start bit).
- if self.state == self.idle_state and self.oldpins == pins:
- continue
-
- self.oldpins, (rx, tx) = pins, pins
-
- if self.options['invert_rx'] == 'yes':
- rx = not rx
- if self.options['invert_tx'] == 'yes':
- tx = not tx
-
- # Either RX or TX (but not both) can be omitted.
- has_pin = [rx in (0, 1), tx in (0, 1)]
- if has_pin == [False, False]:
- raise ChannelError('Either TX or RX (or both) pins required.')
-
- # State machine.
- for rxtx in (RX, TX):
- # Don't try to handle RX (or TX) if not supplied.
- if not has_pin[rxtx]:
- continue
-
- signal = rx if (rxtx == RX) else tx
-
- if self.state[rxtx] == 'WAIT FOR START BIT':
- self.wait_for_start_bit(rxtx, self.oldbit[rxtx], signal)
- elif self.state[rxtx] == 'GET START BIT':
- self.get_start_bit(rxtx, signal)
- elif self.state[rxtx] == 'GET DATA BITS':
- self.get_data_bits(rxtx, signal)
- elif self.state[rxtx] == 'GET PARITY BIT':
- self.get_parity_bit(rxtx, signal)
- elif self.state[rxtx] == 'GET STOP BITS':
- self.get_stop_bits(rxtx, signal)
-
- # Save current RX/TX values for the next round.
- self.oldbit[rxtx] = signal
+
+ has_pin = [self.has_channel(ch) for ch in (RX, TX)]
+ if not True in has_pin:
+ raise ChannelError('Need at least one of TX or RX pins.')
+
+ opt = self.options
+ inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes']
+ cond_data_idx = [None] * len(has_pin)
+
+ # Determine the number of samples for a complete frame's time span.
+ # A period of low signal (at least) that long is a break condition.
+ frame_samples = 1 # START
+ frame_samples += self.options['data_bits']
+ frame_samples += 0 if self.options['parity'] == 'none' else 1
+ frame_samples += self.options['stop_bits']
+ frame_samples *= self.bit_width
+ self.frame_len_sample_count = ceil(frame_samples)
+ self.break_min_sample_count = self.frame_len_sample_count
+ cond_edge_idx = [None] * len(has_pin)
+ cond_idle_idx = [None] * len(has_pin)
+
+ while True:
+ conds = []
+ if has_pin[RX]:
+ cond_data_idx[RX] = len(conds)
+ conds.append(self.get_wait_cond(RX, inv[RX]))
+ cond_edge_idx[RX] = len(conds)
+ conds.append({RX: 'e'})
+ cond_idle_idx[RX] = None
+ idle_cond = self.get_idle_cond(RX, inv[RX])
+ if idle_cond:
+ cond_idle_idx[RX] = len(conds)
+ conds.append(idle_cond)
+ if has_pin[TX]:
+ cond_data_idx[TX] = len(conds)
+ conds.append(self.get_wait_cond(TX, inv[TX]))
+ cond_edge_idx[TX] = len(conds)
+ conds.append({TX: 'e'})
+ cond_idle_idx[TX] = None
+ idle_cond = self.get_idle_cond(TX, inv[TX])
+ if idle_cond:
+ cond_idle_idx[TX] = len(conds)
+ conds.append(idle_cond)
+ (rx, tx) = self.wait(conds)
+ if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]:
+ self.inspect_sample(RX, rx, inv[RX])
+ if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]:
+ self.inspect_edge(RX, rx, inv[RX])
+ self.inspect_idle(RX, rx, inv[RX])
+ if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]:
+ self.inspect_idle(RX, rx, inv[RX])
+ if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]:
+ self.inspect_sample(TX, tx, inv[TX])
+ if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]:
+ self.inspect_edge(TX, tx, inv[TX])
+ self.inspect_idle(TX, tx, inv[TX])
+ if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]:
+ self.inspect_idle(TX, tx, inv[TX])