X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Ftlc5620%2Fpd.py;h=79611540c59c6c95db217f739d1d3a215e50e818;hp=757c30491fd74d79ebed6a3c055c5176f92421e1;hb=6a15597a7b3f901b566b7bfc8c484a14e0fb6a11;hpb=17db40087cb0b4ed76ee26cbc69458f598630fc6

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 757c304..7961154 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# Texas Instruments TLC5620 protocol decoder
-
 import sigrokdecode as srd
 
 dacs = {
@@ -38,19 +36,21 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['tlc5620']
-    probes = [
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
-    ]
-    optional_probes = [
+    )
+    optional_channels = (
         {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
         {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
-    ]
-    options = {}
-    annotations = [
-        ['Text', 'Human-readable text'],
-        ['Warnings', 'Human-readable warnings'],
-    ]
+    )
+    annotations = (
+        ('dac-select', 'DAC select'),
+        ('gain', 'Gain'),
+        ('value', 'DAC value'),
+        ('data-latch', 'Data latch point'),
+        ('ldac-fall', 'LDAC falling edge'),
+    )
 
     def __init__(self, **kwargs):
         self.oldpins = self.oldclk = self.oldload = self.oldldac = None
@@ -61,36 +61,36 @@ class Decoder(srd.Decoder):
         self.ss_value = self.es_value = 0
         self.dac_select = self.gain = self.dac_value = None
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'tlc5620')
-
-    def report(self):
-        pass
+    def start(self):
+        # self.out_python = self.register(srd.OUTPUT_PYTHON)
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_11bits(self):
         s = "".join(str(i) for i in self.bits[:2])
-        self.dac_select = dacs[int(s, 2)]
+        self.dac_select = s = dacs[int(s, 2)]
         self.put(self.ss_dac, self.es_dac, self.out_ann,
-                 [0, ['DAC select: %s' % self.dac_select]])
+                 [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
+                      'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
 
-        self.gain = 1 + self.bits[2]
+        self.gain = g = 1 + self.bits[2]
         self.put(self.ss_gain, self.es_gain, self.out_ann,
-                 [0, ['Gain: x%d' % self.gain]])
+                 [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
 
         s = "".join(str(i) for i in self.bits[3:])
-        self.dac_value = int(s, 2)
+        self.dac_value = v = int(s, 2)
         self.put(self.ss_value, self.es_value, self.out_ann,
-                 [0, ['DAC value: %d' % self.dac_value]])
+                 [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
+                      'V: %d' % v, '%d' % v]])
 
     def handle_falling_edge_load(self):
+        s, v, g = self.dac_select, self.dac_value, self.gain
         self.put(self.samplenum, self.samplenum, self.out_ann,
-                 [0, ['Setting %s value to %d (x%d gain)' % \
-                 (self.dac_select, self.dac_value, self.gain)]])
+                 [3, ['Setting %s value to %d (x%d gain)' % (s, v, g),
+                      '%s=%d (x%d gain)' % (s, v, g)]])
 
     def handle_falling_edge_ldac(self):
         self.put(self.samplenum, self.samplenum, self.out_ann,
-                 [0, ['Falling edge on LDAC pin']])
+                 [4, ['Falling edge on LDAC pin', 'LDAC fall', 'LDAC']])
 
     def handle_new_dac_bit(self):
         self.bits.append(self.datapin)