X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Ftlc5620%2Fpd.py;h=6e7c454df13d30c872eea856a54b9e58821e56d3;hp=71bfb2c16b7aa306cb5e18515d92fb9d82004a10;hb=21b39043472eeeb2e0155eafc73247f5010af714;hpb=92d1aba34bbe661b388e874fda0a41f477d3e30d diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py index 71bfb2c..6e7c454 100644 --- a/decoders/tlc5620/pd.py +++ b/decoders/tlc5620/pd.py @@ -1,5 +1,5 @@ ## -## This file is part of the sigrok project. +## This file is part of the libsigrokdecode project. ## ## Copyright (C) 2012 Uwe Hermann ## @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -# Texas Instruments TLC5620 protocol decoder - import sigrokdecode as srd dacs = { @@ -30,7 +28,7 @@ dacs = { } class Decoder(srd.Decoder): - api_version = 1 + api_version = 2 id = 'tlc5620' name = 'TI TLC5620' longname = 'Texas Instruments TLC5620' @@ -38,49 +36,76 @@ class Decoder(srd.Decoder): license = 'gplv2+' inputs = ['logic'] outputs = ['tlc5620'] - probes = [ + channels = ( {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, - ] - optional_probes = [ + ) + optional_channels = ( {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, - ] - options = {} - annotations = [ - ['Text', 'Human-readable text'], - ['Warnings', 'Human-readable warnings'], - ] + ) + annotations = ( + ('dac-select', 'DAC select'), + ('gain', 'Gain'), + ('value', 'DAC value'), + ('data-latch', 'Data latch point'), + ('ldac-fall', 'LDAC falling edge'), + ) def __init__(self, **kwargs): - self.state = 'IDLE' - self.oldpins = None - self.oldclk = None + self.oldpins = self.oldclk = self.oldload = self.oldldac = None + self.datapin = None self.bits = [] self.ss_dac = self.es_dac = 0 self.ss_gain = self.es_gain = 0 self.ss_value = self.es_value = 0 + self.dac_select = self.gain = self.dac_value = None - def start(self, metadata): - # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620') - self.out_ann = self.add(srd.OUTPUT_ANN, 'tlc5620') - - def report(self): - pass + def start(self): + self.out_ann = self.register(srd.OUTPUT_ANN) def handle_11bits(self): - s = "".join(str(i) for i in self.bits[:2]) + s = ''.join(str(i) for i in self.bits[:2]) + self.dac_select = s = dacs[int(s, 2)] self.put(self.ss_dac, self.es_dac, self.out_ann, - [0, ['DAC select: %s' % dacs[int(s, 2)]]]) + [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, + 'DAC: %s' % s, 'D: %s' % s, s, s[3]]]) + self.gain = g = 1 + self.bits[2] self.put(self.ss_gain, self.es_gain, self.out_ann, - [0, ['Gain: x%d' % (1 + self.bits[2])]]) + [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) - s = "".join(str(i) for i in self.bits[3:]) + s = ''.join(str(i) for i in self.bits[3:]) + self.dac_value = v = int(s, 2) self.put(self.ss_value, self.es_value, self.out_ann, - [0, ['DAC value: %d' % int(s, 2)]]) - - self.bits = [] + [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v, + 'V: %d' % v, '%d' % v]]) + + def handle_falling_edge_load(self): + s, v, g = self.dac_select, self.dac_value, self.gain + self.put(self.samplenum, self.samplenum, self.out_ann, + [3, ['Setting %s value to %d (x%d gain)' % (s, v, g), + '%s=%d (x%d gain)' % (s, v, g)]]) + + def handle_falling_edge_ldac(self): + self.put(self.samplenum, self.samplenum, self.out_ann, + [4, ['Falling edge on LDAC pin', 'LDAC fall', 'LDAC']]) + + def handle_new_dac_bit(self): + self.bits.append(self.datapin) + + # Wait until we have read 11 bits, then parse them. + l, s = len(self.bits), self.samplenum + if l == 1: + self.ss_dac = s + elif l == 2: + self.es_dac = self.ss_gain = s + elif l == 3: + self.es_gain = self.ss_value = s + elif l == 11: + self.es_value = s + self.handle_11bits() + self.bits = [] def decode(self, ss, es, data): for (self.samplenum, pins) in data: @@ -88,31 +113,19 @@ class Decoder(srd.Decoder): # Ignore identical samples early on (for performance reasons). if self.oldpins == pins: continue - self.oldpins, (clk, data, load, ldac) = pins, pins + self.oldpins, (clk, self.datapin, load, ldac) = pins, pins # DATA is shifted in the DAC on the falling CLK edge (MSB-first). - # TODO: Handle various LOAD-/LDAC-controlled methods. - if not (self.oldclk == 1 and clk == 0): - self.oldclk = clk - continue + # A falling edge of LOAD will latch the data. - # The DAC has received a new bit, store it. - self.bits.append(data) - - if self.state == 'IDLE': - # Wait until we have read 11 bits, then parse them. - l, s = len(self.bits), self.samplenum - if l == 1: - self.ss_dac = s - elif l == 2: - self.es_dac = self.ss_gain = s - elif l == 3: - self.es_gain = self.ss_value = s - elif l == 11: - self.es_value = s - self.handle_11bits() - else: - raise Exception('Invalid state: %s' % self.state) + if self.oldload == 1 and load == 0: + self.handle_falling_edge_load() + if self.oldldac == 1 and ldac == 0: + self.handle_falling_edge_ldac() + if self.oldclk == 1 and clk == 0: + self.handle_new_dac_bit() self.oldclk = clk + self.oldload = load + self.oldldac = ldac