X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Ftlc5620%2Fpd.py;h=4d02792c6091dfbe4f2437262b3f76c425a36271;hp=886d5c9ce60cb4af24d3dccbf0e7ce73ae15f78d;hb=6cbba91f23b9f9ace75b4722c9c0776b9211008d;hpb=ce0c47f34659181a7c5f82bfb782d8a5f5987ac7 diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py index 886d5c9..4d02792 100644 --- a/decoders/tlc5620/pd.py +++ b/decoders/tlc5620/pd.py @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -28,14 +27,15 @@ dacs = { } class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'tlc5620' name = 'TI TLC5620' longname = 'Texas Instruments TLC5620' desc = 'Texas Instruments TLC5620 8-bit quad DAC.' license = 'gplv2+' inputs = ['logic'] - outputs = ['tlc5620'] + outputs = [] + tags = ['IC', 'Analog/digital'] channels = ( {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, @@ -44,6 +44,12 @@ class Decoder(srd.Decoder): {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, ) + options = ( + {'id': 'vref_a', 'desc': 'Reference voltage DACA (V)', 'default': 3.3}, + {'id': 'vref_b', 'desc': 'Reference voltage DACB (V)', 'default': 3.3}, + {'id': 'vref_c', 'desc': 'Reference voltage DACC (V)', 'default': 3.3}, + {'id': 'vref_d', 'desc': 'Reference voltage DACD (V)', 'default': 3.3}, + ) annotations = ( ('dac-select', 'DAC select'), ('gain', 'Gain'), @@ -51,28 +57,60 @@ class Decoder(srd.Decoder): ('data-latch', 'Data latch point'), ('ldac-fall', 'LDAC falling edge'), ('bit', 'Bit'), - ('operation', 'Operation'), + ('reg-write', 'Register write'), + ('voltage-update', 'Voltage update'), + ('voltage-update-all', 'Voltage update (all DACs)'), + ('invalid-cmd', 'Invalid command'), ) annotation_rows = ( ('bits', 'Bits', (5,)), ('fields', 'Fields', (0, 1, 2)), - ('operations', 'Operations', (6,)), + ('registers', 'Registers', (6, 7)), + ('voltage-updates', 'Voltage updates', (8,)), ('events', 'Events', (3, 4)), + ('errors', 'Errors', (9,)), ) - def __init__(self, **kwargs): - self.oldpins = self.oldclk = self.oldload = self.oldldac = None - self.datapin = None + def __init__(self): + self.reset() + + def reset(self): self.bits = [] + self.ss_dac_first = None self.ss_dac = self.es_dac = 0 self.ss_gain = self.es_gain = 0 self.ss_value = self.es_value = 0 self.dac_select = self.gain = self.dac_value = None + self.dacval = {'A': '?', 'B': '?', 'C': '?', 'D': '?'} + self.gains = {'A': '?', 'B': '?', 'C': '?', 'D': '?'} def start(self): self.out_ann = self.register(srd.OUTPUT_ANN) def handle_11bits(self): + # Only look at the last 11 bits, the rest is ignored by the TLC5620. + if len(self.bits) > 11: + self.bits = self.bits[-11:] + + # If there are less than 11 bits, something is probably wrong. + if len(self.bits) < 11: + ss, es = self.samplenum, self.samplenum + if len(self.bits) >= 2: + ss = self.bits[0][1] + es = self.bits[-1][1] + (self.bits[1][1] - self.bits[0][1]) + self.put(ss, es, self.out_ann, [9, ['Command too short']]) + self.bits = [] + return False + + self.ss_dac = self.bits[0][1] + self.es_dac = self.ss_gain = self.bits[2][1] + self.es_gain = self.ss_value = self.bits[3][1] + self.clock_width = self.es_gain - self.ss_gain + self.es_value = self.bits[10][1] + self.clock_width # Guessed. + + if self.ss_dac_first is None: + self.ss_dac_first = self.ss_dac + s = ''.join(str(i[0]) for i in self.bits[:2]) self.dac_select = s = dacs[int(s, 2)] self.put(self.ss_dac, self.es_dac, self.out_ann, @@ -96,53 +134,76 @@ class Decoder(srd.Decoder): self.put(self.bits[10][1], self.bits[10][1] + self.clock_width, self.out_ann, [5, [str(self.bits[10][0])]]) + self.bits = [] + + return True + def handle_falling_edge_load(self): + if not self.handle_11bits(): + return s, v, g = self.dac_select, self.dac_value, self.gain self.put(self.samplenum, self.samplenum, self.out_ann, [3, ['Falling edge on LOAD', 'LOAD fall', 'F']]) - self.put(self.ss_dac, self.es_value, self.out_ann, - [6, ['Setting %s value to %d (x%d gain)' % (s, v, g), - '%s=%d (x%d gain)' % (s, v, g)]]) + vref = self.options['vref_%s' % self.dac_select[3].lower()] + v = '%.2fV' % (vref * (v / 256) * self.gain) + if self.ldac == 0: + # If LDAC is low, the voltage is set immediately. + self.put(self.ss_dac, self.es_value, self.out_ann, + [7, ['Setting %s voltage to %s' % (s, v), + '%s=%s' % (s, v)]]) + else: + # If LDAC is high, the voltage is not set immediately, but rather + # stored in a register. When LDAC goes low all four DAC voltages + # (DAC A/B/C/D) will be set at the same time. + self.put(self.ss_dac, self.es_value, self.out_ann, + [6, ['Setting %s register value to %s' % \ + (s, v), '%s=%s' % (s, v)]]) + # Save the last value the respective DAC was set to. + self.dacval[self.dac_select[-1]] = str(self.dac_value) + self.gains[self.dac_select[-1]] = self.gain def handle_falling_edge_ldac(self): self.put(self.samplenum, self.samplenum, self.out_ann, [4, ['Falling edge on LDAC', 'LDAC fall', 'LDAC', 'L']]) - def handle_new_dac_bit(self): - self.bits.append([self.datapin, self.samplenum]) - - # Wait until we have read 11 bits, then parse them. - l, s = len(self.bits), self.samplenum - if l == 1: - self.ss_dac = s - elif l == 3: - self.es_dac = self.ss_gain = s - elif l == 4: - self.es_gain = self.ss_value = s - self.clock_width = self.es_gain - self.ss_gain - elif l == 11: - self.es_value = s + self.clock_width # Guessed. - self.handle_11bits() - self.bits = [] - - def decode(self, ss, es, data): - for (self.samplenum, pins) in data: - - # Ignore identical samples early on (for performance reasons). - if self.oldpins == pins: - continue - self.oldpins, (clk, self.datapin, load, ldac) = pins, pins - + # Don't emit any annotations if we didn't see any register writes. + if self.ss_dac_first is None: + return + + # Calculate voltages based on Vref and the per-DAC gain. + dacval = {} + for key, val in self.dacval.items(): + if val == '?': + dacval[key] = '?' + else: + vref = self.options['vref_%s' % key.lower()] + v = vref * (int(val) / 256) * self.gains[key] + dacval[key] = '%.2fV' % v + + s = ''.join(['DAC%s=%s ' % (d, dacval[d]) for d in 'ABCD']).strip() + self.put(self.ss_dac_first, self.samplenum, self.out_ann, + [8, ['Updating voltages: %s' % s, s, s.replace('DAC', '')]]) + self.ss_dac_first = None + + def handle_new_dac_bit(self, datapin): + self.bits.append([datapin, self.samplenum]) + + def decode(self): + while True: # DATA is shifted in the DAC on the falling CLK edge (MSB-first). # A falling edge of LOAD will latch the data. - if self.oldload == 1 and load == 0: + # Wait for one (or multiple) of the following conditions: + # a) Falling edge on CLK, and/or + # b) Falling edge on LOAD, and/or + # b) Falling edge on LDAC + pins = self.wait([{0: 'f'}, {2: 'f'}, {3: 'f'}]) + self.ldac = pins[3] + + # Handle those conditions (one or more) that matched this time. + if self.matched[0]: + self.handle_new_dac_bit(pins[1]) + if self.matched[1]: self.handle_falling_edge_load() - if self.oldldac == 1 and ldac == 0: + if self.matched[2]: self.handle_falling_edge_ldac() - if self.oldclk == 1 and clk == 0: - self.handle_new_dac_bit() - - self.oldclk = clk - self.oldload = load - self.oldldac = ldac