X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Ftlc5620%2Fpd.py;h=1487f917ac3b58a0c50fdf0b07928079a2e4e176;hp=61f6028f5a58c774fe525fd4a117acf34130be37;hb=c761524941fcb2237ceb65082e504e5e48e62a05;hpb=7fb4935edde881272fabdeda83f554bcf150689f

diff --git a/decoders/tlc5620/pd.py b/decoders/tlc5620/pd.py
index 61f6028..1487f91 100644
--- a/decoders/tlc5620/pd.py
+++ b/decoders/tlc5620/pd.py
@@ -18,8 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-# Texas Instruments TLC5620 protocol decoder
-
 import sigrokdecode as srd
 
 dacs = {
@@ -38,22 +36,21 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['tlc5620']
-    probes = [
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
         {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
-    ]
-    optional_probes = [
+    )
+    optional_channels = (
         {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
         {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
-    ]
-    options = {}
-    annotations = [
-        ['dac_select', 'DAC select'],
-        ['gain', 'Gain'],
-        ['value', 'DAC value'],
-        ['data_latch', 'Data latch point'],
-        ['ldac_fall', 'LDAC falling edge'],
-    ]
+    )
+    annotations = (
+        ('dac-select', 'DAC select'),
+        ('gain', 'Gain'),
+        ('value', 'DAC value'),
+        ('data-latch', 'Data latch point'),
+        ('ldac-fall', 'LDAC falling edge'),
+    )
 
     def __init__(self, **kwargs):
         self.oldpins = self.oldclk = self.oldload = self.oldldac = None
@@ -64,12 +61,8 @@ class Decoder(srd.Decoder):
         self.ss_value = self.es_value = 0
         self.dac_select = self.gain = self.dac_value = None
 
-    def start(self, metadata):
-        # self.out_proto = self.add(srd.OUTPUT_PROTO, 'tlc5620')
-        self.out_ann = self.add(srd.OUTPUT_ANN, 'tlc5620')
-
-    def report(self):
-        pass
+    def start(self):
+        self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def handle_11bits(self):
         s = "".join(str(i) for i in self.bits[:2])