X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fswd%2Fpd.py;h=22aad4533d25b89aba66f55edabbd4058b195156;hp=d53d1493f59d7f9e6fb867dede91a4cae71dbffa;hb=4539e9ca58966ce3c9cad4801b16c315e86ace01;hpb=1483fb220ce56405433aee298d1637f6b041ac2b;ds=sidebyside diff --git a/decoders/swd/pd.py b/decoders/swd/pd.py index d53d149..22aad45 100644 --- a/decoders/swd/pd.py +++ b/decoders/swd/pd.py @@ -14,8 +14,7 @@ ## GNU General Public License for more details. ## ## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## along with this program; if not, see . ## import sigrokdecode as srd @@ -65,7 +64,7 @@ BIT_CTRLSTAT_ORUNDETECT = 1 ANNOTATIONS = ['reset', 'enable', 'read', 'write', 'ack', 'data', 'parity'] class Decoder(srd.Decoder): - api_version = 2 + api_version = 3 id = 'swd' name = 'SWD' longname = 'Serial Wire Debug' @@ -92,10 +91,9 @@ class Decoder(srd.Decoder): ('parity', 'PARITY'), ) - def __init__(self, **kwargs): + def __init__(self): # SWD data/clock state self.state = 'UNKNOWN' - self.oldclk = -1 self.sample_edge = RISING self.ack = None # Ack state of the current phase self.ss_req = 0 # Start sample of current req @@ -142,11 +140,10 @@ class Decoder(srd.Decoder): }[(self.apdp, self.rw)] self.putp(ptype, (self.addr, self.data, self.ack)) - def decode(self, ss, es, data): - for (self.samplenum, (clk, dio)) in data: - if clk == self.oldclk: - continue # Not a clock edge. - self.oldclk = clk + def decode(self): + while True: + # Wait for any clock edge. + clk, dio = self.wait({0: 'e'}) # Count rising edges with DIO held high, # as a line reset (50+ high edges) can happen from any state.