X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fswd%2Fpd.py;h=0f7bc22aab281eaa8b418604f6970131a5524d69;hp=3414c35f7cf3a17eff4548522f32e5a1fa57d406;hb=039b0db244e2e592a581a6c9b79a934bde136569;hpb=92b7b49f6964f57a7d6fc4473645c993cfa4ba52

diff --git a/decoders/swd/pd.py b/decoders/swd/pd.py
index 3414c35..0f7bc22 100644
--- a/decoders/swd/pd.py
+++ b/decoders/swd/pd.py
@@ -14,8 +14,7 @@
 ## GNU General Public License for more details.
 ##
 ## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## along with this program; if not, see <http://www.gnu.org/licenses/>.
 ##
 
 import sigrokdecode as srd
@@ -65,7 +64,7 @@ BIT_CTRLSTAT_ORUNDETECT = 1
 ANNOTATIONS = ['reset', 'enable', 'read', 'write', 'ack', 'data', 'parity']
 
 class Decoder(srd.Decoder):
-    api_version = 2
+    api_version = 3
     id = 'swd'
     name = 'SWD'
     longname = 'Serial Wire Debug'
@@ -93,9 +92,11 @@ class Decoder(srd.Decoder):
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         # SWD data/clock state
         self.state = 'UNKNOWN'
-        self.oldclk = -1
         self.sample_edge = RISING
         self.ack = None # Ack state of the current phase
         self.ss_req = 0 # Start sample of current req
@@ -142,11 +143,10 @@ class Decoder(srd.Decoder):
         }[(self.apdp, self.rw)]
         self.putp(ptype, (self.addr, self.data, self.ack))
 
-    def decode(self, ss, es, data):
-        for (self.samplenum, (clk, dio)) in data:
-            if clk == self.oldclk:
-                continue # Not a clock edge.
-            self.oldclk = clk
+    def decode(self):
+        while True:
+            # Wait for any clock edge.
+            clk, dio = self.wait({0: 'e'})
 
             # Count rising edges with DIO held high,
             # as a line reset (50+ high edges) can happen from any state.