X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspiflash%2Fpd.py;h=5ee22740553efa2ca69ca1cef1f93a02d25006d1;hp=8e2b041225876f2e376359f51694be840de16739;hb=6cbba91f23b9f9ace75b4722c9c0776b9211008d;hpb=b197383cfb39b39ff04644855eef57f5d3c18bc1 diff --git a/decoders/spiflash/pd.py b/decoders/spiflash/pd.py index 8e2b041..5ee2274 100644 --- a/decoders/spiflash/pd.py +++ b/decoders/spiflash/pd.py @@ -25,8 +25,8 @@ L = len(cmds) # Don't forget to keep this in sync with 'cmds' is lists.py. class Ann: WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \ - RDSR2, CE, ESRY, DSRY, REMS, RDID, RDP_RES, CP, ENSO, DP, READ2X, \ - EXSO, CE2, BE, REMS2, \ + RDSR2, CE, ESRY, DSRY, WRITE1, WRITE2, REMS, RDID, RDP_RES, CP, ENSO, DP, \ + READ2X, EXSO, CE2, STATUS, BE, REMS2, \ BIT, FIELD, WARN = range(L + 3) def cmd_annotation_classes(): @@ -78,7 +78,8 @@ class Decoder(srd.Decoder): desc = 'xx25 series SPI (NOR) flash chip protocol.' license = 'gplv2+' inputs = ['spi'] - outputs = ['spiflash'] + outputs = [] + tags = ['IC', 'Memory'] annotations = cmd_annotation_classes() + ( ('bit', 'Bit'), ('field', 'Field'), @@ -98,9 +99,13 @@ class Decoder(srd.Decoder): ) def __init__(self): + self.reset() + + def reset(self): self.device_id = -1 self.on_end_transaction = None self.end_current_transaction() + self.writestate = 0 # Build dict mapping command keys to handler functions. Each # command in 'cmds' (defined in lists.py) has a matching @@ -171,10 +176,11 @@ class Decoder(srd.Decoder): def handle_wren(self, mosi, miso): self.putx([Ann.WREN, self.cmd_ann_list()]) - self.state = None + self.writestate = 1 def handle_wrdi(self, mosi, miso): - pass # TODO + self.putx([Ann.WRDI, self.cmd_ann_list()]) + self.writestate = 0 def handle_rdid(self, mosi, miso): if self.cmdstate == 1: @@ -212,6 +218,8 @@ class Decoder(srd.Decoder): self.putx([Ann.BIT, [decode_status_reg(miso)]]) self.putx([Ann.FIELD, ['Status register']]) self.putc([Ann.RDSR, self.cmd_ann_list()]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 self.cmdstate += 1 def handle_rdsr2(self, mosi, miso): @@ -241,12 +249,14 @@ class Decoder(srd.Decoder): self.emit_cmd_byte() elif self.cmdstate == 2: # Byte 2: Master sends status register 1. - self.putx([Ann.BIT, [decode_status_reg(miso)]]) + self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 1']]) + # Set write latch state. + self.writestate = 1 if (miso & (1 << 1)) else 0 elif self.cmdstate == 3: # Byte 3: Master sends status register 2. # TODO: Decode status register 2 correctly. - self.putx([Ann.BIT, [decode_status_reg(miso)]]) + self.putx([Ann.BIT, [decode_status_reg(mosi)]]) self.putx([Ann.FIELD, ['Status register 2']]) self.es_cmd = self.es self.putc([Ann.WRSR, self.cmd_ann_list()]) @@ -270,6 +280,32 @@ class Decoder(srd.Decoder): self.data.append(miso) self.cmdstate += 1 + def handle_write_common(self, mosi, miso, ann): + # Write data bytes: Master asserts CS#, sends WRITE command, sends + # 3-byte address, writes >= 1 data bytes, de-asserts CS#. + if self.cmdstate == 1: + # Byte 1: Master sends command ID. + self.emit_cmd_byte() + if self.writestate == 0: + self.putc([Ann.WARN, ['Warning: WREN might be missing']]) + elif self.cmdstate in (2, 3, 4): + # Bytes 2/3/4: Master sends write address (24bits, MSB-first). + self.emit_addr_bytes(mosi) + elif self.cmdstate >= 5: + # Bytes 5-x: Master writes data bytes (until CS# de-asserted). + self.es_field = self.es # Will be overwritten for each byte. + if self.cmdstate == 5: + self.ss_field = self.ss + self.on_end_transaction = lambda: self.output_data_block('Data', ann) + self.data.append(mosi) + self.cmdstate += 1 + + def handle_write1(self, mosi, miso): + self.handle_write_common(mosi, miso, Ann.WRITE1) + + def handle_write2(self, mosi, miso): + self.handle_write_common(mosi, miso, Ann.WRITE2) + def handle_fast_read(self, mosi, miso): # Fast read: Master asserts CS#, sends FAST READ command, sends # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#. @@ -321,12 +357,27 @@ class Decoder(srd.Decoder): self.data.append(b2) self.cmdstate += 1 + def handle_status(self, mosi, miso): + if self.cmdstate == 1: + # Byte 1: Master sends command ID. + self.emit_cmd_byte() + self.on_end_transaction = lambda: self.putc([Ann.STATUS, [cmds[self.state][1]]]) + else: + # Will be overwritten for each byte. + self.es_cmd = self.es + self.es_field = self.es + if self.cmdstate == 2: + self.ss_field = self.ss + self.putx([Ann.BIT, ['Status register byte %d: 0x%02x' % ((self.cmdstate % 2) + 1, miso)]]) + self.cmdstate += 1 + # TODO: Warn/abort if we don't see the necessary amount of bytes. - # TODO: Warn if WREN was not seen before. def handle_se(self, mosi, miso): if self.cmdstate == 1: # Byte 1: Master sends command ID. self.emit_cmd_byte() + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) elif self.cmdstate in (2, 3, 4): # Bytes 2/3/4: Master sends sector address (24bits, MSB-first). self.emit_addr_bytes(mosi) @@ -347,10 +398,14 @@ class Decoder(srd.Decoder): pass # TODO def handle_ce(self, mosi, miso): - pass # TODO + self.putx([Ann.CE, self.cmd_ann_list()]) + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) def handle_ce2(self, mosi, miso): - pass # TODO + self.putx([Ann.CE2, self.cmd_ann_list()]) + if self.writestate == 0: + self.putx([Ann.WARN, ['Warning: WREN might be missing']]) def handle_pp(self, mosi, miso): # Page program: Master asserts CS#, sends PP command, sends 3-byte @@ -419,8 +474,8 @@ class Decoder(srd.Decoder): self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) if self.cmdstate == 6: - id = self.ids[1] if self.manufacturer_id_first else self.ids[0] - self.device_id = id + id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0] + self.device_id = id_ self.es_cmd = self.es self.putc([Ann.REMS, self.cmd_vendor_dev_list()]) self.state = None