X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fspi.py;h=5e5e74ec5c7123d8a022beb0086e04a7e1f17dc8;hp=bbf0f3705af62f9762794d3e19cf064ccd84f793;hb=4180cba9a51acd32f69f0f8628bb746ea3e12be6;hpb=94bbdb9a4146ec5eaa56411706dc92de3a92f2d8

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index bbf0f37..5e5e74e 100644
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+# SPI protocol decoder
+
 import sigrokdecode as srd
 
 # Key: (CPOL, CPHA). Value: SPI mode.
@@ -40,7 +42,6 @@ class Decoder(srd.Decoder):
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
     desc = '...desc...'
-    longdesc = '...longdesc...'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -82,9 +83,7 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
-
-            self.samplenum += 1 # FIXME
+        for (self.samplenum, (miso, mosi, sck, cs)) in data:
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -105,7 +104,7 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
+                self.start_sample = self.samplenum
                 active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted: