X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fspi.py;h=10857866f4cad8ebdc41fe58600cdb688b8d6420;hp=a2ae86f2821a9695dd02a267ba489d6de6253da9;hb=2fcd7c22852436c3226de9007e88cb305cce1b00;hpb=122e9a90a54e034b93f554938896983d293edec1

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index a2ae86f..1085786 100644
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -41,7 +41,7 @@ class Decoder(srd.Decoder):
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
-    desc = '...desc...'
+    desc = 'Full-duplex, synchronous, serial bus.'
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
@@ -73,6 +73,8 @@ class Decoder(srd.Decoder):
         self.bytesreceived = 0
         self.samplenum = -1
         self.cs_was_deasserted_during_data_word = 0
+        self.oldcs = -1
+        self.oldpins = None
 
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
@@ -83,9 +85,20 @@ class Decoder(srd.Decoder):
 
     def decode(self, ss, es, data):
         # TODO: Either MISO or MOSI could be optional. CS# is optional.
-        for (samplenum, (miso, mosi, sck, cs)) in data:
+        for (self.samplenum, pins) in data:
 
-            self.samplenum += 1 # FIXME
+            # Ignore identical samples early on (for performance reasons).
+            if self.oldpins == pins:
+                continue
+            self.oldpins, (miso, mosi, sck, cs) = pins, pins
+
+            if self.oldcs != cs:
+                # Send all CS# pin value changes.
+                self.put(self.samplenum, self.samplenum, self.out_proto,
+                         ['CS-CHANGE', self.oldcs, cs])
+                self.put(self.samplenum, self.samplenum, self.out_ann,
+                         [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]])
+                self.oldcs = cs
 
             # Ignore sample if the clock pin hasn't changed.
             if sck == self.oldsck:
@@ -106,7 +119,7 @@ class Decoder(srd.Decoder):
 
             # If this is the first bit, save its sample number.
             if self.bitcount == 0:
-                self.start_sample = samplenum
+                self.start_sample = self.samplenum
                 active_low = (self.options['cs_polarity'] == 'active-low')
                 deasserted = cs if active_low else not cs
                 if deasserted:
@@ -133,7 +146,7 @@ class Decoder(srd.Decoder):
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,
-                     ['data', self.mosidata, self.misodata])
+                     ['DATA', self.mosidata, self.misodata])
             self.put(self.start_sample, self.samplenum, self.out_ann,
                      [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
                      self.misodata)]])