X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fspi.py;h=10857866f4cad8ebdc41fe58600cdb688b8d6420;hp=5e5e74ec5c7123d8a022beb0086e04a7e1f17dc8;hb=2fcd7c22852436c3226de9007e88cb305cce1b00;hpb=4180cba9a51acd32f69f0f8628bb746ea3e12be6 diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py index 5e5e74e..1085786 100644 --- a/decoders/spi/spi.py +++ b/decoders/spi/spi.py @@ -41,7 +41,7 @@ class Decoder(srd.Decoder): id = 'spi' name = 'SPI' longname = 'Serial Peripheral Interface' - desc = '...desc...' + desc = 'Full-duplex, synchronous, serial bus.' license = 'gplv2+' inputs = ['logic'] outputs = ['spi'] @@ -73,6 +73,8 @@ class Decoder(srd.Decoder): self.bytesreceived = 0 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 + self.oldcs = -1 + self.oldpins = None def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') @@ -83,7 +85,20 @@ class Decoder(srd.Decoder): def decode(self, ss, es, data): # TODO: Either MISO or MOSI could be optional. CS# is optional. - for (self.samplenum, (miso, mosi, sck, cs)) in data: + for (self.samplenum, pins) in data: + + # Ignore identical samples early on (for performance reasons). + if self.oldpins == pins: + continue + self.oldpins, (miso, mosi, sck, cs) = pins, pins + + if self.oldcs != cs: + # Send all CS# pin value changes. + self.put(self.samplenum, self.samplenum, self.out_proto, + ['CS-CHANGE', self.oldcs, cs]) + self.put(self.samplenum, self.samplenum, self.out_ann, + [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]]) + self.oldcs = cs # Ignore sample if the clock pin hasn't changed. if sck == self.oldsck: @@ -131,7 +146,7 @@ class Decoder(srd.Decoder): continue self.put(self.start_sample, self.samplenum, self.out_proto, - ['data', self.mosidata, self.misodata]) + ['DATA', self.mosidata, self.misodata]) self.put(self.start_sample, self.samplenum, self.out_ann, [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, self.misodata)]])