X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fspi.py;h=10857866f4cad8ebdc41fe58600cdb688b8d6420;hp=25cfcfa3fc390bdb2ca08dd2c48bc57a2cce0ce2;hb=2fcd7c22852436c3226de9007e88cb305cce1b00;hpb=a2c2afd9357fab233a4f09531618faa81d54d4d9 diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py index 25cfcfa..1085786 100644 --- a/decoders/spi/spi.py +++ b/decoders/spi/spi.py @@ -19,24 +19,13 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -import sigrokdecode as srd - -# Chip-select options -ACTIVE_LOW = 0 -ACTIVE_HIGH = 1 - -# Clock polarity options -CPOL_0 = 0 # Clock is low when inactive -CPOL_1 = 1 # Clock is high when inactive - -# Clock phase options -CPHA_0 = 0 # Data is valid on the leading clock edge -CPHA_1 = 1 # Data is valid on the trailing clock edge +# SPI protocol decoder -# Bit order options -MSB_FIRST = 0 -LSB_FIRST = 1 +import sigrokdecode as srd +# Key: (CPOL, CPHA). Value: SPI mode. +# Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. +# Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. spi_mode = { (0, 0): 0, # Mode 0 (0, 1): 1, # Mode 1 @@ -52,24 +41,24 @@ class Decoder(srd.Decoder): id = 'spi' name = 'SPI' longname = 'Serial Peripheral Interface' - desc = '...desc...' - longdesc = '...longdesc...' + desc = 'Full-duplex, synchronous, serial bus.' license = 'gplv2+' inputs = ['logic'] outputs = ['spi'] probes = [ - {'id': 'mosi', 'name': 'MOSI', - 'desc': 'SPI MOSI line (Master out, slave in)'}, {'id': 'miso', 'name': 'MISO', 'desc': 'SPI MISO line (Master in, slave out)'}, + {'id': 'mosi', 'name': 'MOSI', + 'desc': 'SPI MOSI line (Master out, slave in)'}, {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, ] + optional_probes = [] # TODO options = { - 'cs_polarity': ['CS# polarity', ACTIVE_LOW], - 'cpol': ['Clock polarity', CPOL_0], - 'cpha': ['Clock phase', CPHA_0], - 'bitorder': ['Bit order within the SPI data', MSB_FIRST], + 'cs_polarity': ['CS# polarity', 'active-low'], + 'cpol': ['Clock polarity', 0], + 'cpha': ['Clock phase', 0], + 'bitorder': ['Bit order within the SPI data', 'msb-first'], 'wordsize': ['Word size of SPI data', 8], # 1-64? } annotations = [ @@ -84,13 +73,8 @@ class Decoder(srd.Decoder): self.bytesreceived = 0 self.samplenum = -1 self.cs_was_deasserted_during_data_word = 0 - - # Set protocol decoder option defaults. - self.cs_polarity = Decoder.options['cs_polarity'][1] - self.cpol = Decoder.options['cpol'][1] - self.cpha = Decoder.options['cpha'][1] - self.bitorder = Decoder.options['bitorder'][1] - self.wordsize = Decoder.options['wordsize'][1] + self.oldcs = -1 + self.oldpins = None def start(self, metadata): self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') @@ -100,13 +84,21 @@ class Decoder(srd.Decoder): return 'SPI: %d bytes received' % self.bytesreceived def decode(self, ss, es, data): - # HACK! At the moment the number of probes is not handled correctly. - # E.g. if an input file (-i foo.sr) has more than two probes enabled. - # for (samplenum, (mosi, sck, x, y, z, a)) in data: - # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: - for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: + # TODO: Either MISO or MOSI could be optional. CS# is optional. + for (self.samplenum, pins) in data: - self.samplenum += 1 # FIXME + # Ignore identical samples early on (for performance reasons). + if self.oldpins == pins: + continue + self.oldpins, (miso, mosi, sck, cs) = pins, pins + + if self.oldcs != cs: + # Send all CS# pin value changes. + self.put(self.samplenum, self.samplenum, self.out_proto, + ['CS-CHANGE', self.oldcs, cs]) + self.put(self.samplenum, self.samplenum, self.out_ann, + [0, ['CS-CHANGE: %d->%d' % (self.oldcs, cs)]]) + self.oldcs = cs # Ignore sample if the clock pin hasn't changed. if sck == self.oldsck: @@ -115,7 +107,7 @@ class Decoder(srd.Decoder): self.oldsck = sck # Sample data on rising/falling clock edge (depends on mode). - mode = spi_mode[self.cpol, self.cpha] + mode = spi_mode[self.options['cpol'], self.options['cpha']] if mode == 0 and sck == 0: # Sample on rising clock edge continue elif mode == 1 and sck == 1: # Sample on falling clock edge @@ -127,31 +119,34 @@ class Decoder(srd.Decoder): # If this is the first bit, save its sample number. if self.bitcount == 0: - self.start_sample = samplenum - deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c + self.start_sample = self.samplenum + active_low = (self.options['cs_polarity'] == 'active-low') + deasserted = cs if active_low else not cs if deasserted: self.cs_was_deasserted_during_data_word = 1 + ws = self.options['wordsize'] + # Receive MOSI bit into our shift register. - if self.bitorder == MSB_FIRST: - self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount) + if self.options['bitorder'] == 'msb-first': + self.mosidata |= mosi << (ws - 1 - self.bitcount) else: self.mosidata |= mosi << self.bitcount # Receive MISO bit into our shift register. - if self.bitorder == MSB_FIRST: - self.misodata |= miso << (self.wordsize - 1 - self.bitcount) + if self.options['bitorder'] == 'msb-first': + self.misodata |= miso << (ws - 1 - self.bitcount) else: self.misodata |= miso << self.bitcount self.bitcount += 1 - # Continue to receive if not a byte yet. - if self.bitcount != self.wordsize: + # Continue to receive if not enough bits were received, yet. + if self.bitcount != ws: continue self.put(self.start_sample, self.samplenum, self.out_proto, - ['data', self.mosidata, self.misodata]) + ['DATA', self.mosidata, self.misodata]) self.put(self.start_sample, self.samplenum, self.out_ann, [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, self.misodata)]])