X-Git-Url: https://sigrok.org/gitweb/?p=libsigrokdecode.git;a=blobdiff_plain;f=decoders%2Fspi%2Fpd.py;h=9beb4e63b2642358b7447881e22a2fe0376208ed;hp=09b5689650efdbe68865024a12bdb816aafc8e70;hb=866a80dbed40dcd295efd4c7f28288b7835c973d;hpb=92a06d0b6bbe173257d7c76ed2318f5b35f65637
diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 09b5689..9beb4e6 100644
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -15,11 +15,13 @@
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+## along with this program; if not, see .
##
import sigrokdecode as srd
+from collections import namedtuple
+
+Data = namedtuple('Data', ['ss', 'es', 'val'])
'''
OUTPUT_PYTHON format:
@@ -38,6 +40,9 @@ Packet:
Both data items are Python numbers (0/1), not strings. At the beginning of
the decoding a packet is generated with = None and being the
initial state of the CS# pin or None if the chip select pin is not supplied.
+ - 'TRANSFER': / contain a list of Data() namedtuples for each
+ byte transferred during this block of CS# asserted time. Each Data() has
+ fields ss, es, and val.
Examples:
['CS-CHANGE', None, 1]
@@ -51,6 +56,8 @@ Examples:
['DATA', 0xa8, None]
['DATA', None, 0x55]
['CS-CHANGE', 0, 1]
+ ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...],
+ [Data(ss=80, es=96, val=0x3a), ...]]
'''
# Key: (CPOL, CPHA). Value: SPI mode.
@@ -63,14 +70,11 @@ spi_mode = {
(1, 1): 3, # Mode 3
}
-class SamplerateError(Exception):
- pass
-
class ChannelError(Exception):
pass
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'spi'
name = 'SPI'
longname = 'Serial Peripheral Interface'
@@ -117,19 +121,21 @@ class Decoder(srd.Decoder):
)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
- self.oldclk = 1
self.bitcount = 0
self.misodata = self.mosidata = 0
self.misobits = []
self.mosibits = []
+ self.misobytes = []
+ self.mosibytes = []
self.ss_block = -1
self.samplenum = -1
+ self.ss_transfer = -1
self.cs_was_deasserted = False
- self.oldcs = None
- self.oldpins = None
self.have_cs = self.have_miso = self.have_mosi = None
- self.no_cs_notification = False
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
@@ -138,9 +144,11 @@ class Decoder(srd.Decoder):
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
- self.out_bin = self.register(srd.OUTPUT_BINARY)
- self.out_bitrate = self.register(srd.OUTPUT_META,
- meta=(int, 'Bitrate', 'Bitrate during transfers'))
+ self.out_binary = self.register(srd.OUTPUT_BINARY)
+ if self.samplerate:
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
+ self.bw = (self.options['wordsize'] + 7) // 8
def putw(self, data):
self.put(self.ss_block, self.samplenum, self.out_ann, data)
@@ -154,14 +162,21 @@ class Decoder(srd.Decoder):
if self.have_miso:
ss, es = self.misobits[-1][1], self.misobits[0][2]
- self.put(ss, es, self.out_bin, (0, bytes([so])))
+ bdata = so.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [0, bdata])
if self.have_mosi:
ss, es = self.mosibits[-1][1], self.mosibits[0][2]
- self.put(ss, es, self.out_bin, (1, bytes([si])))
+ bdata = si.to_bytes(self.bw, byteorder='big')
+ self.put(ss, es, self.out_binary, [1, bdata])
self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
self.put(ss, es, self.out_python, ['DATA', si, so])
+ if self.have_miso:
+ self.misobytes.append(Data(ss=ss, es=es, val=so))
+ if self.have_mosi:
+ self.mosibytes.append(Data(ss=ss, es=es, val=si))
+
# Bit annotations.
if self.have_miso:
for bit in self.misobits:
@@ -195,17 +210,18 @@ class Decoder(srd.Decoder):
not self.cs_asserted(cs) if self.have_cs else False
ws = self.options['wordsize']
+ bo = self.options['bitorder']
# Receive MISO bit into our shift register.
if self.have_miso:
- if self.options['bitorder'] == 'msb-first':
+ if bo == 'msb-first':
self.misodata |= miso << (ws - 1 - self.bitcount)
else:
self.misodata |= miso << self.bitcount
# Receive MOSI bit into our shift register.
if self.have_mosi:
- if self.options['bitorder'] == 'msb-first':
+ if bo == 'msb-first':
self.mosidata |= mosi << (ws - 1 - self.bitcount)
else:
self.mosidata |= mosi << self.bitcount
@@ -237,22 +253,32 @@ class Decoder(srd.Decoder):
self.putdata()
# Meta bitrate.
- elapsed = 1 / float(self.samplerate)
- elapsed *= (self.samplenum - self.ss_block + 1)
- bitrate = int(1 / elapsed * self.options['wordsize'])
- self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
+ if self.samplerate:
+ elapsed = 1 / float(self.samplerate)
+ elapsed *= (self.samplenum - self.ss_block + 1)
+ bitrate = int(1 / elapsed * ws)
+ self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
if self.have_cs and self.cs_was_deasserted:
self.putw([4, ['CS# was deasserted during this data word!']])
self.reset_decoder_state()
- def find_clk_edge(self, miso, mosi, clk, cs):
- if self.have_cs and self.oldcs != cs:
+ def find_clk_edge(self, miso, mosi, clk, cs, first):
+ if self.have_cs and (first or self.matched[self.have_cs]):
# Send all CS# pin value changes.
+ oldcs = None if first else 1 - cs
self.put(self.samplenum, self.samplenum, self.out_python,
- ['CS-CHANGE', self.oldcs, cs])
- self.oldcs = cs
+ ['CS-CHANGE', oldcs, cs])
+
+ if self.cs_asserted(cs):
+ self.ss_transfer = self.samplenum
+ self.misobytes = []
+ self.mosibytes = []
+ else:
+ self.put(self.ss_transfer, self.samplenum, self.out_python,
+ ['TRANSFER', self.mosibytes, self.misobytes])
+
# Reset decoder state when CS# changes (and the CS# pin is used).
self.reset_decoder_state()
@@ -261,11 +287,9 @@ class Decoder(srd.Decoder):
return
# Ignore sample if the clock pin hasn't changed.
- if clk == self.oldclk:
+ if first or not self.matched[0]:
return
- self.oldclk = clk
-
# Sample data on rising/falling clock edge (depends on mode).
mode = spi_mode[self.options['cpol'], self.options['cpha']]
if mode == 0 and clk == 0: # Sample on rising clock edge
@@ -280,27 +304,35 @@ class Decoder(srd.Decoder):
# Found the correct clock edge, now get the SPI bit(s).
self.handle_bit(miso, mosi, clk, cs)
- def decode(self, ss, es, data):
- if not self.samplerate:
- raise SamplerateError('Cannot decode without samplerate.')
- # Either MISO or MOSI can be omitted (but not both). CS# is optional.
- for (self.samplenum, pins) in data:
-
- # Ignore identical samples early on (for performance reasons).
- if self.oldpins == pins:
- continue
- self.oldpins, (clk, miso, mosi, cs) = pins, pins
- self.have_miso = (miso in (0, 1))
- self.have_mosi = (mosi in (0, 1))
- self.have_cs = (cs in (0, 1))
-
- # Either MISO or MOSI (but not both) can be omitted.
- if not (self.have_miso or self.have_mosi):
- raise ChannelError('Either MISO or MOSI (or both) pins required.')
-
- # Tell stacked decoders that we don't have a CS# signal.
- if not self.no_cs_notification and not self.have_cs:
- self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
- self.no_cs_notification = True
-
- self.find_clk_edge(miso, mosi, clk, cs)
+ def decode(self):
+ # The CLK input is mandatory. Other signals are (individually)
+ # optional. Yet either MISO or MOSI (or both) must be provided.
+ # Tell stacked decoders when we don't have a CS# signal.
+ if not self.has_channel(0):
+ raise ChannelError('Either MISO or MOSI (or both) pins required.')
+ self.have_miso = self.has_channel(1)
+ self.have_mosi = self.has_channel(2)
+ if not self.have_miso and not self.have_mosi:
+ raise ChannelError('Either MISO or MOSI (or both) pins required.')
+ self.have_cs = self.has_channel(3)
+ if not self.have_cs:
+ self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
+
+ # We want all CLK changes. We want all CS changes if CS is used.
+ # Map 'have_cs' from boolean to an integer index. This simplifies
+ # evaluation in other locations.
+ wait_cond = [{0: 'e'}]
+ if self.have_cs:
+ self.have_cs = len(wait_cond)
+ wait_cond.append({3: 'e'})
+
+ # "Pixel compatibility" with the v2 implementation. Grab and
+ # process the very first sample before checking for edges. The
+ # previous implementation did this by seeding old values with
+ # None, which led to an immediate "change" in comparison.
+ (clk, miso, mosi, cs) = self.wait({})
+ self.find_clk_edge(miso, mosi, clk, cs, True)
+
+ while True:
+ (clk, miso, mosi, cs) = self.wait(wait_cond)
+ self.find_clk_edge(miso, mosi, clk, cs, False)